Intel SL22U Bedienungsanleitung
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Intel® 64 Architecture x2APIC
Specification
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ReReference Number: 318148-004
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Developers must not rely on the absence or characteristics of any features or instructions marked “re-
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Copyright © 2006-2010 Intel Corporation
1-1
INTRODUCTION
CHAPTER 1
INTRODUCTION
1.1 INTRODUCTION
The xAPIC architecture provided a key mechanism for interrupt delivery in many
generations of Intel processors and platforms across different market segments. This
document describes the x2APIC architecture which is extended from the xAPIC archi-
tecture (the latter was first implemented on Intel® Pentium® 4 Processors, and
extended the APIC architecture implemented on Pentium and P6 processors). Exten-
sions to the xAPIC architecture are intended primarily to increase processor addres-
sability. The x2APIC architecture provides backward compatibility to the xAPIC
architecture and forward extendability for future Intel platform innovations. Specifi-
cally, x2APIC
•Retains all key elements of compatibility to the xAPIC architecture:
— delivery modes,
— interrupt and processor priorities,
— interrupt sources,
— interrupt destination types;
•Provides extensions to scale processor addressability for both the logical and
physical destination modes;
•Adds new features to enhance performance of interrupt delivery;
•Reduces complexity of logical destination mode interrupt delivery on link based
architectures.
1.2 IMPACTED PLATFORM COMPONENTS
x2APIC is architected to extend from the xAPIC architecture while minimizing the
impact on platform components. Specifically, support for the x2APIC architecture can
be implemented in the local APIC unit. All existing PCI/MSI capable devices and
IOxAPIC unit should work with the x2APIC extensions defined in this document. The
x2APIC architecture also provides flexibility to cope with the underlying fabrics that
connect the PCI devices, IOxAPICs and Local APIC units.
The extensions provided in this specification translate into modifications to:
•the local APIC unit,
•the underlying fabrics connecting Message Signaled Interrupts (MSI) capable PCI
devices to local xAPICs,
•the underlying fabrics connecting the IOxAPICs to the local APIC units.
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