Intel i7-2960XM Bedienungsanleitung

Intel Prozessor i7-2960XM

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Document Number: 320835-003
Intel® Core™ i7-900 Desktop
Processor Extreme Edition Series
and Intel® Core™ i7-900 Desktop
Processor Series
Datasheet, Volume 2
October 2009
2 Datasheet
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,
BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
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AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING
LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY
PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or
life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
The Intel® Core™ i7-900 desktop processor Extreme Edition series and Intel ® Core™ i7-900 desktop processor series may contain
design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor
family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time
processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not
intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number
progression is not necessarily representative of future roadmaps. See www.intel.com/products/processor_number for details.
Hyper-Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology-
enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. For
more information including details on which processors support HT Technology, see
http://www.intel.com/products/ht/hyperthreading_more.htm
Intel® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled
for Intel® 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary
depending on your hardware and software configurations. See www.intel.com/info/em64t for more information including details on
which processors support Intel® 64 or consult with your system vendor for more information.
± Intel® Virtualization Technology requires a computer system with a processor, chipset, BIOS, virtual machine monitor (VMM) and
for some uses, certain platform software, enabled for it. Functionality, performance or other benefit will vary depending on
hardware and software configurations. Intel Virtualization Technology-enabled VMM applications are currently in development.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting
operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
Enhanced Intel® SpeedStep Technology. See the Processor Spec Finder or contact your Intel representative for more information.
Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost
Technology performance varies depending on hardware, software and overall system configuration. Check with your PC
manufacturer on whether your system delivers Intel Turbo Boost Technology. For more information, see www.intel.com .
Intel, Xeon, Enhanced Intel SpeedStep Technology and the Intel logo are trademarks of Intel Corporation in the United States and
other countries.
*Other brands and names are the property of their respective owners.
Copyright © 2008–2009, Intel Corporation.
Datasheet 3
Contents
1 Introduction ............................................................................................................ 11
1.1 Terminology ..................................................................................................... 11
1.1.1 Processor Terminology .......................................................................... 11
1.2 References ....................................................................................................... 13
2 Register Description ................................................................................................ 15
2.1 Register Terminology ......................................................................................... 15
2.2 Platform Configuration Structure ......................................................................... 16
2.3 Device Mapping................................................................................................. 17
2.4 Detailed Configuration Space Maps ...................................................................... 18
2.5 PCI Standard Registers ...................................................................................... 36
2.5.1 VID - Vendor Identification Register ........................................................ 36
2.5.2 DID - Device Identification Register......................................................... 36
2.5.3 RID - Revision Identification Register....................................................... 37
2.5.4 CCR - Class Code Register ..................................................................... 37
2.5.5 HDR - Header Type Register................................................................... 38
2.5.6 SID/SVID - Subsystem Identity/Subsystem Vendor
Identification Register ........................................................................... 38
2.5.7 PCICMD - Command Register ................................................................. 39
2.5.8 PCISTS - PCI Status Register.................................................................. 40
2.6 SAD - System Address Decoder Registers ............................................................. 41
2.6.1 SAD_PAM0123 ..................................................................................... 41
2.6.2 SAD_PAM456 ....................................................................................... 43
2.6.3 SAD_HEN ............................................................................................ 44
2.6.4 SAD_SMRAM ........................................................................................ 44
2.6.5 SAD_PCIEXBAR .................................................................................... 45
2.6.6 SAD_DRAM_RULE_0, SAD_DRAM_RULE_1, SAD_DRAM_RULE_2,
SAD_DRAM_RULE_3
SAD_DRAM_RULE_4, SAD_DRAM_RULE_5
SAD_DRAM_RULE_6, SAD_DRAM_RULE_7 ............................................... 45
2.6.7 SAD_INTERLEAVE_LIST_0, SAD_INTERLEAVE_LIST_1
SAD_INTERLEAVE_LIST_2, SAD_INTERLEAVE_LIST_3
SAD_INTERLEAVE_LIST_4, SAD_INTERLEAVE_LIST_5
SAD_INTERLEAVE_LIST_6, SAD_INTERLEAVE_LIST_7 ............................... 46
2.7 Intel QPI Link Registers...................................................................................... 47
2.7.1 QPI_QPILCL_L0, QPI_QPILCL_L1 ............................................................ 47
2.8 Integrated Memory Controller Control Registers .................................................... 47
2.8.1 MC_CONTROL ...................................................................................... 47
2.8.2 MC_STATUS......................................................................................... 49
2.8.3 MC_SMI_SPARE_DIMM_ERROR_STATUS.................................................. 50
2.8.4 MC_SMI_SPARE_CNTRL......................................................................... 51
2.8.5 MC_RESET_CONTROL............................................................................ 51
2.8.6 MC_CHANNEL_MAPPER.......................................................................... 52
2.8.7 MC_MAX_DOD...................................................................................... 53
2.8.8 MC_RD_CRDT_INIT............................................................................... 54
2.8.9 MC_CRDT_WR_THLD............................................................................. 55
2.8.10 MC_SCRUBADDR_LO............................................................................. 55
2.8.11 MC_SCRUBADDR_HI ............................................................................. 56
2.9 TAD – Target Address Decoder Registers .............................................................. 57
2.9.1 TAD_DRAM_RULE_0, TAD_DRAM_RULE_1
TAD_DRAM_RULE_2, TAD_DRAM_RULE_3
TAD_DRAM_RULE_4, TAD_DRAM_RULE_5
TAD_DRAM_RULE_6, TAD_DRAM_RULE_7................................................ 57


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