Texas Instruments TPA3110D2PWP Bedienungsanleitung

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LINP
LINN
RINP
RINN
SDSD
FaultFault
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PBTL
PVCC 8to26V
1 Fm
OUTNL
OUTPL 15W
FERRITE
BEAD
FILTER 8W
OUTR+
OUTR-
OUTL+
OUTL-
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TPA3110D2
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OUTNR
OUTPR 15W
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FERRITE
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPA3110D2
SLOS528F – JULY 2009 – REVISED APRIL 2017
TPA3110D2 15-W Fil ter-Free Stereo Class-D Audio Power Amplier With Speakerguard
1
1 Features
1
15-W/ch into an 8- Loads at 10% THD+N From
a 16-V Supply
10-W/ch into 8- Loads at 10% THD+N From a
13-V Supply
30-W into a 4- Mono Load at 10% THD+N From
a 16-V Supply
90% Ecient Class-D Operation Eliminates Need
for Heat Sinks
Wide Supply Voltage Range Allows Operation
From 8 V to 26 V
Filter-Free Operation
SpeakerGuard™ Speaker Protection Includes
Adjustable Power Limiter Plus DC Protection
Flow Through Pin Out Facilitates Easy Board
Layout
Robust Pin-to-Pin Short Circuit Protection and
Thermal Protection With Auto Recovery Option
Excellent THD+N / Pop-Free Performance
Four Selectable, Fixed Gain Settings
Dierential Inputs
2 Applications
• Televisions
Consumer Audio Equipment
3 Description
The TPA3110D2 is a 15-W (per channel) ecient,
Class-D audio power amplier for driving bridged-tied
stereo speakers. Advanced EMI Suppression
Technology enables the use of inexpensive ferrite
bead lters at the outputs while meeting EMC
requirements. SpeakerGuard™ speaker protection
circuitry includes an adjustable power limiter and a
DC detection circuit. The adjustable power limiter
allows the user to set a "virtual" voltage rail lower
than the chip supply to limit the amount of current
through the speaker. The DC detect circuit measures
the frequency and amplitude of the PWM signal and
shuts o the output stage if the input capacitors are
damaged or shorts exist on the inputs.
The TPA3110D2 can drive stereo speakers as low as
4 . The high eciency of the TPA3110D2, 90%,
eliminates the need for an external heat sink when
playing music.
The outputs are also fully protected against shorts to
GND, VCC, and output-to-output. The short-circuit
protection and thermal protection includes an auto-
recovery feature.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPA3110D2 HTSSOP (28) 9.70 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
TPA3110D2 Simplied Application Schematic
2
TPA3110D2
SLOS528F – JULY 2009 – REVISED APRIL 2017
www.ti.com
Product Folder Links: TPA3110D2
Submit Documentation Feedback Copyright © 2009–2017, Texas Instruments Incorporated
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Device Comparison Table..................................... 4
6 Pin Conguration and F unctions........................ 4
7 Specications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions ...................... 6
7.4 Thermal Information.................................................. 6
7.5 DC Characteristics: 24 V.......................................... 6
7.6 DC Characteristics: 12 V.......................................... 7
7.7 AC Characteristics: 24 V.......................................... 7
7.8 AC Characteristics: 12 V.......................................... 7
7.9 Typical Characteristics ............................................. 8
8 Parameter Measurement Information ................ 14
9 Detailed Description ............................................ 14
9.1 Overview ................................................................. 14
9.2 Functional Block Diagram ....................................... 14
9.3 Feature Description................................................. 15
9.4 Device Functional Modes........................................ 20
10 Application and Implementation........................ 21
10.1 Application Information.......................................... 21
10.2 Typical Applications ............................................. 21
11 Power Supply Recommendations ..................... 25
11.1 Power Supply Decoupling, C
S............................. 25
12 Layout................................................................... 25
12.1 Layout Guidelines ................................................. 25
12.2 Layout Example .................................................... 26
13 Device and Documentation Support ................. 27
13.1 Device Support .................................................... 27
13.2 Documentation Support ........................................ 27
13.3 Community Resources.......................................... 27
13.4 Trademarks ........................................................... 27
13.5 Electrostatic Discharge Caution............................ 27
13.6 Glossary ................................................................ 27
14 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may dier from page numbers in the current version.
Changes from Revision E (November 2015) to Revision F Page
Added Measurement note added to characterization graphs............................................................................................... 10
Added New Output Power vs Supply Voltage Characterization graph ................................................................................ 10
Added footnote for heatsink and EVM ................................................................................................................................. 14
Changes from Revision D (July 2012) to Revision E Page
• Added section, table, section,Pin Conguration and Functions ESD Ratings Feature Description Device Functional
Modes Application and Implementation Power Supply Recommendations Layout Device, section, section, section,
and Documentation Support Mechanical, Packaging, and Orderable Informationsection, and section .............................. 1
Changes from Revision C (August 2010) to Revision D Page
Added < 10 V/ms to VIin the Absolute Maximum Ratings table, added Note 2 .................................................................... 5
Changed the PBTL Select section. Added text - "The voltage slew.......series with the terminals." .................................... 19
Added a 100k resistor to AVCC Pin 14 and Note 1 to ......................................................................................ΩFigure 46 24
Changes from Revision B (July 2010) to Revision C Page
Replaced the Dissipations Ratings table with the Thermal Information table ........................................................................ 6
Changes from Revision A (July 2009) to Revision B Page
Added slew rate adjustment information .............................................................................................................................. 17
Added AVCC to Pin 7 of ......................................................................................................................................Figure 46 24
3
TPA3110D2
www.ti.com
SLOS528F – JULY 2009 – REVISED APRIL 2017
Product Folder Links: TPA3110D2
Submit Documentation FeedbackCopyright © 2009–2017, Texas Instruments Incorporated
Changes from Original (July 2009) to Revision A Page
Changed Changed the Stereo Class-D Amplier with BTL Output and Single-Ended Input illustration -Figure 42
Corrected the pin names. ..................................................................................................................................................... 21
Changed Changed the Stereo Class-D Amplier with PBTL Output and Single-Ended Input illustration -Figure 46
Corrected the pin names. ..................................................................................................................................................... 24

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