Texas Instruments SN74LS241DW Bedienungsanleitung


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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LS240
,
SN54LS241
,
SN54LS244
,
SN54S240
,
SN54S241
,
SN54S244
SN74LS240
,
SN74LS241
,
SN74LS244
,
SN74S240
,
SN74S241
,
SN74S244
SDLS144D –APRIL 1985 REVISED OCTOBER 2016
SNx4LS24x, SNx4S24x Octal Buers and Line Drivers With 3-State Outputs
1
1 Features
1
Inputs Tolerant Down to 2 V, Compatible With
3.3-V or 2.5-V Logic Inputs
Maximum tpd of 15 ns at 5 V
3-State Outputs Drive Bus Lines or Buer Memory
Address Registers
PNP Inputs Reduce DC Loading
Hysteresis at Inputs Improves Noise Margins
2 Applications
• Servers
LED Displays
Network Switches
Telecom Infrastructure
Motor Drivers
I/O Expanders
3 Description
The SNx4LS24x, SNx4S24x octal buers and line
drivers are designed specically to improve both the
performance and density of three-state memory
address drivers, clock drivers, and bus-oriented
receivers and transmitters. The designer has a choice
of selected combinations of inverting and non-
inverting outputs, symmetrical, active-low output-
control (G) inputs, and complementary output-control
(G and G) inputs. These devices feature high fan-out,
improved fan-in, and 400-mV noise margin. The
SN74LS24x and SN74S24x devices can be used to
drive terminated lines down to 133 .Ω
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN54LS24x,
SN54S24x
CDIP (20) – J 24.20 mm × 6.92 mm
CFP (20) – W 7.02 mm × 13.72 mm
LCCC (20) – FK 8.89 mm × 8.89 mm
SN74LS240,
SN74LS244 SSOP (20) – DB 7.20 mm × 5.30 mm
SN74LS24x,
SN74S24x
SOIC (20) DW 12.80 mm × 7.50 mm
PDIP (20) – N 24.33 mm × 6.35 mm
SN74LS24x SOP (20) – NS 7.80 mm × 12.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
2
SN54LS240
,
SN54LS241
,
SN54LS244
,
SN54S240
,
SN54S241
,
SN54S244
SN74LS240
,
SN74LS241
,
SN74LS244
,
SN74S240
,
SN74S241
,
SN74S244
SDLS144D – APRIL 1985 – REVISED OCTOBER 2016
www.ti.com
Product Folder Links: SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240
SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244
Submit Documentation Feedback Copyright © 1985–2016, Texas Instruments Incorporated
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Conguration and Functions ......................... 3
6 Specications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information ................................................. 5
6.5 Electrical Characteristics – SNx4LS24x.................... 5
6.6 Electrical Characteristics – SNx4S24x...................... 5
6.7 Switching Characteristics – SNx4LS24x ................... 6
6.8 Switching Characteristics – SNx4S24x..................... 6
6.9 Typical Characteristics.............................................. 7
7 Parameter Measurement Information .................. 7
7.1 SN54LS24x and SN74LS24x Devices...................... 7
7.2 SN54S24x and SN74S24x Devices.......................... 9
8 Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagrams ..................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 12
9 Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application .................................................. 14
9.3 System Examples ................................................... 15
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1 Related Links ........................................................ 18
12.2 Receiving Notication of Documentation Updates 18
12.3 Community Resource............................................ 18
12.4 Trademarks ........................................................... 18
12.5 Electrostatic Discharge Caution............................ 18
12.6 Glossary ................................................................ 18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may dier from page numbers in the current version.
Changes from Revision C (May 2010) to Revision D Page
• Added section, table, section, ,Applications ESD Ratings Feature Description Device Functional Modes Application
and Implementation Power Supply Recommendations Layout Device and Documentationsection, section, section,
Support Mechanical, Packaging, and Orderable Informationsection, and section................................................................ 1
Deleted Ordering Information table; see POA at the end of the data sheet........................................................................... 1
Changed RθJA values in the table from 70 to 94.3 (DB), from 58 to 90.3 (DW), from 69 to 50.6Thermal Information
(N), and from 60 to 76.6 (NS)................................................................................................................................................. 5
41A2
52Y3
61A3
72Y2
81A4
92Y1
10GND
112A1
121Y4
132A2
14 1Y3
15 2A3
16 1Y2
17 2A4
18 1Y1
19 2G/2G
20 VCC
1 1G
2 1A1
3 2Y4
Not to scale
11G 20 VCC
21A1 19 2G/2G
32Y4 18 1Y1
41A2 17 2A4
52Y3 16 1Y2
61A3 15 2A3
72Y2 14 1Y3
81A4 13 2A2
92Y1 12 1Y4
10GND 11 2A1
Not to scale
3
SN54LS240
,
SN54LS241
,
SN54LS244
,
SN54S240
,
SN54S241
,
SN54S244
SN74LS240
,
SN74LS241
,
SN74LS244
,
SN74S240
,
SN74S241
,
SN74S244
www.ti.com
SDLS144D – APRIL 1985 – REVISED OCTOBER 2016
Product Folder Links: SN54LS240 SN54LS241 SN54LS244 SN54S240 SN54S241 SN54S244 SN74LS240
SN74LS241 SN74LS244 SN74S240 SN74S241 SN74S244
Submit Documentation FeedbackCopyright © 1985–2016, Texas Instruments Incorporated
5 Pin Conguration and Functions
DB, DW, J, N, NS, or W Package
20-Pin SSOP, SOIC, CDIP, PDIP, SOP, or CFP
Top View
FK Package
20-Pin LCCC
Top View
(1) 2G for SNx4LS241 and SNx4S241 or 2G for all other drivers.
Pin Functions
PIN I/O DESCRIPTION
NO. NAME
1 1G I Channel 1 output enable
2 1A1 I Channel 1, A side 1
3 2Y4 O Channel 2, Y side 4
4 1A2 I Channel 1, A side 2
5 2Y3 O Channel 2, Y side 3
6 1A3 I Channel 1, A side 3
7 2Y2 O Channel 2, Y side 2
8 1A4 I Channel 1, A side 4
9 2Y1 O Channel 2, Y side 1
10 GND — Ground
11 2A1 I Channel 2, A side 1
12 1Y4 O Channel 1, Y side 4
13 2A2 I Channel 2, A side 2
14 1Y3 O Channel 1, Y side 3
15 2A3 I Channel 2, A side 3
16 1Y2 O Channel 1, Y side 2
17 2A4 I Channel 2, A side 4
18 1Y1 O Channel 1, Y side 1
19 2G/2G(1) I Channel 2 output enable
20 VCC Power supply


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Modell: SN74LS241DW

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