Texas Instruments SN74CBT16245CDL Bedienungsanleitung


Lesen Sie kostenlos die πŸ“– deutsche Bedienungsanleitung fΓΌr Texas Instruments SN74CBT16245CDL (18 Seiten) in der Kategorie Nicht kategorisiert. Dieser Bedienungsanleitung war fΓΌr 18 Personen hilfreich und wurde von 2 Benutzern mit durchschnittlich 4.5 Sternen bewertet

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SCDS139 βˆ’ OCTOBER 2003
1
POST OFFICE BOX 655303 β€’ DALLAS, TEXAS 75265
DMember of the Texas Instruments
Widebusο£ͺ Family
DUndershoot Protection for O-Isolation on
A and B Ports Up to βˆ’2 V
DBidirectional Data Flow, With Near-Zero
Propagation Delay
DLow ON-State Resistance (ron)
Characteristics (ron = 3 Ω Typical)
DLow Input/Output Capacitance Minimizes
Loading and Signal Distortion
(Cio(OFF) = 5.5 pF Typical)
DData and Control Inputs Provide
Undershoot Clamp Diodes
DLow Power Consumption
(ICC = 3 A Max)Β΅
DVCC Operating Range From 4 V to 5.5 V
DData I/Os Support 0 to 5-V Signaling Levels
(0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
DControl Inputs Can be Driven by TTL or
5-V/3.3-V CMOS Outputs
DIoff Supports Partial-Power-Down Mode
Operation
DLatch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DESD Performance Tested Per JESD 22
βˆ’ 2000-V Human-Body Model
(A114-B, Class II)
βˆ’ 1000-V Charged-Device Model (C101)
DSupports Both Digital and Analog
Applications: PCI Interface, Memory
Interleaving, Bus Isolation, Low-Distortion
Signal Gating
description/ordering information
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SSOP DL
Tube SN74CBT16245CDL
CBT16245C
SSOP βˆ’ DL Tape and reel SN74CBT16245CDLR CBT16245C
βˆ’40Β° Β°C to 85 C
TSSOP DGG
Tube SN74CBT16245CDGG
CBT16245C
TSSOP βˆ’ DGG
Tape and reel SN74CBT16245CDGGR
CBT16245C
TVSOP βˆ’ DGV Tape and reel SN74CBT16245CDGVR CY245C
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright  2003, Texas Instruments Incorporated
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1
2
3
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NC
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
NC
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
NC βˆ’ No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Widebus is a trademark of Texas Instruments.
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ξ˜ˆξ˜‰ξ˜Œξ˜†ξ˜ξ˜‡ ξ˜Žξ˜ξ˜‡ ξ˜†ξ˜ξ˜ ξ˜ξ˜‘ξ˜ξ˜‡ξ˜…ξ˜’
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SCDS139 βˆ’ OCTOBER 2003
2POST OFFICE BOX 655303 β€’ DALLAS, TEXAS 75265
description/ordering information (continued)
The SN74CBT16245C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r on),
allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the
SN74CBT16245C provides protection for undershoot up to βˆ’2 V by sensing an undershoot event and ensuring
that the switch remains in the proper OFF state.
The SN74CBT16245C is organized as two 8-bit bus switches with separate output-enable (1OE , 2OE) inputs.
It can be used as two 8-bit bus switches or as one 16-bit bus switch. When OE is low, the associated 8-bit bus
switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When
OE is high, the associated 8-bit bus switch is OFF and the high-impedance state exists between the A and B
ports.
This device is fully speciξ‹ˆed for partial-power-down applications using Ioff. The Ioff feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each 8-bit bus switch)
INPUT
INPUT/OUTPUT
FUNCTION
INPUT
OE
INPUT/OUTPUT
A
FUNCTION
L B A port = B port
H Z Disconnect
logic diagram (positive logic)
1A1 SW 1B1
1A8
1OE
SW 1B8
2A1 SW 2B1
2A8
2OE
SW 2B8
47
37
48
36
26
25
2
12
13
23
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ξ˜ˆξ˜‰ξ˜Œξ˜†ξ˜ξ˜‡ ξ˜Žξ˜ξ˜‡ ξ˜†ξ˜ξ˜ ξ˜ξ˜‘ξ˜ξ˜‡ξ˜…ξ˜’
ξ˜‹ξ˜Œξ˜“ ξ˜†ξ˜ξ˜ ξ˜ξ˜‘ξ˜ξ˜‡ξ˜…ξ˜’ ξ˜‘ξ˜ξ˜‡ξ˜’ ξ˜”ξ˜Šξ˜Œξ˜“ ξ˜ξ˜‚ξ˜•ξ˜ξ˜–ξ˜ξ˜’ξ˜—ξ˜—ξ˜‡ ξ˜˜ξ˜–ξ˜— ξ˜‡ ξ˜ξ˜…ξ˜‡ξ˜ ξ˜—ξ˜‚
SCDS139 βˆ’ OCTOBER 2003
3
POST OFFICE BOX 655303 β€’ DALLAS, TEXAS 75265
simplified schematic, each FET switch (SW)
A
EN†
B
†EN is the internal enable signal applied to the switch.
Undershoot
Protection Circuit
absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ‑
Supply voltage range, VCC βˆ’0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control input voltage range, VIN (see Notes 1 and 2) βˆ’0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switch I/O voltage range, VI/O
(see Notes 1, 2, and 3) βˆ’0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control input clamp current, IIK (VIN < 0) βˆ’50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O port clamp current, II/OK (VI/O < 0) βˆ’50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ON-state switch current, II/O (see Note 4) Β±128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND terminals Β±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, ΞΈJA (see Note 5): DGG package 70Β°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 58Β°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 63Β°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg βˆ’65Β° Β°C to 150 C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‑Stresses beyond those listed under β€œabsolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under β€œrecommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. VI and VO are used to denote specific conditions for V
I/O.
4. II and I
O are used to denote specific conditions for I
I/O.
5. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 6)
MIN MAX UNIT
VCC Supply voltage 4 5.5 V
VIH High-level control input voltage 2 5.5 V
VIL Low-level control input voltage 0 0.8 V
VI/O Data input/output voltage 0 5.5 V
TAOperating free-air temperature βˆ’40 85 CΒ°
NOTE 6: All unused control inputs of the device must be held at V
CC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.


Produktspezifikationen

Marke: Texas Instruments
Kategorie: Nicht kategorisiert
Modell: SN74CBT16245CDL
Breite: 16 mm
Tiefe: 7.59 mm
HΓΆhe: 2.54 mm
Betriebstemperatur: -40 - 85 Β°C
Verpackungsbreite: 14.24 mm
Verpackungstiefe: 473.7 mm
VerpackungshΓΆhe: 5.11 mm
Typ: Logik-IC
Menge pro Packung: 25 StΓΌck(e)
Verpackungsart: SSOP
Temperaturbereich bei Lagerung: -65 - 150 Β°C
Anzahl Pins: 48
Breite (mit Pins): 16 mm
Tiefe (mit Pins): 10.67 mm
HΓΆhe (mit Pins): 2.79 mm

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