Texas Instruments SN74AVC2T45DCTT Bedienungsanleitung

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DIR 5

A1 2

VCCA VCCB

A2 3

VCCA VCCB

GND4

VCCA VCCB

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN74AVC2T45

SCES531L –DECEMBER 2003 – REVISED MAY 2017

SN74AVC2T45 2-Bit, Dual Supply, Bus Transceiver

With Congurable Level-Shifting and Translation

1 Features

• Available in the Texas Instruments NanoFree™

Package

• VCC Isolation Feature: If Either VCC Input Is at

GND, Both Ports Are in the High-Impedance State

• Dual Supply Rail Design

• I/Os Are 4.6-V Over Voltage Tolerant

• Io Supports Partial-Power-Down Mode Operation

• Max Data Rates

– 500 Mbps (1.8 V to 3.3 V)

– 320 Mbps (<1.8 V to 3.3 V )

– 320 Mbps (Level-Shifting to 2.5 V or 1.8 V)

– 280 Mbps (Level-Shifting to 1.5 V)

– 240 Mbps (Level-Shifting to 1.2 V)

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Protection Exceeds JESD 22

2 Applications

• Smartphones

• Servers

• Desktop PCs and Notebooks

• Other Portable Devices

3 Description

This 2-bit non-inverting bus transceiver uses two

separate congurable power-supply rails. The A ports

are designed to track VCCA and accepts any supply

voltage from 1.2 V to 3.6 V. The B ports are designed

to track VCCB and accepts any supply voltage from

1.2 V to 3.6 V. This allows for universal low-voltage

bidirectional translation and level-shifting between

any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V

voltage nodes.

The SN74AVC2T45 is designed for asynchronous

communication between two data buses. The logic

levels of the direction-control (DIR pin) input activate

either the B-port outputs or the A-port outputs. The

device transmits data from the A bus to the B bus

when the B-port outputs are activated and from the B

bus to the A bus when the A-port outputs are

activated. The input circuitry on both A and B ports

always is active and must have a logic HIGH or LOW

level applied to prevent excess leakage current on

the internal CMOS structure.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

SN74AVC2T45DCT SM8 (8) 2.95 mm × 2.80 mm

SN74AVC2T45DCU VSSOP (8) 2.30 mm × 2.00 mm

SN74AVC2T45YZP DSBGA (8) 1.89 mm × 0.89 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Logic Diagram (Positive Logic)

(1) Pin numbers are for the DCT and DCU packages only.

SN74AVC2T45

SCES531L – DECEMBER 2003 – REVISED MAY 2017

www.ti.com

Product Folder Links: SN74AVC2T45

Table of Contents

1 Features .................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Conguration and Functions ......................... 3

6 Specications......................................................... 4

6.1 Absolute Maximum Ratings ..................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

6.6 Switching Characteristics: V

CCA = 1.2 V ................... 7

6.7 Switching Characteristics: V

CCA = 1.5 V ±0.1 V........ 7

6.8 Switching Characteristics: V

CCA = 1.8 V ±0.15 V...... 8

6.9 Switching Characteristics: V

CCA = 2.5 V ±0.2 V........ 8

6.10 Switching Characteristics: V

CCA = 3.3 V ±0.3 V...... 9

6.11 Operating Characteristics........................................ 9

6.12 Typical Characteristics .......................................... 10

7 Parameter Measurement Information ................ 12

8 Detailed Description ............................................ 13

8.1 Overview ................................................................. 13

8.2 Functional Block Diagram ....................................... 13

8.3 Feature Description................................................. 14

8.4 Device Functional Modes........................................ 14

9 Application and Implementation ........................ 15

9.1 Application Information............................................ 15

9.2 Typical Applications ................................................ 15

10 Power Supply Recommendations ..................... 18

11 Layout................................................................... 18

11.1 Layout Guidelines ................................................. 18

11.2 Layout Example .................................................... 18

12 Device and Documentation Support ................. 19

12.1 Documentation Support ........................................ 19

12.2 Receiving Notication of Documentation Updates 19

12.3 Community Resources.......................................... 19

12.4 Trademarks ........................................................... 19

12.5 Electrostatic Discharge Caution............................ 19

12.6 Glossary ................................................................ 19

13 Mechanical, Packaging, and Orderable

Information ........................................................... 19

4 Revision History

NOTE: Page numbers for previous revisions may dier from page numbers in the current version.

Changes from Revision K (April 2015) to Revision L Page

• Changed data sheet title......................................................................................................................................................... 1

• Changed YZP package pinout diagram to bottom view ......................................................................................................... 3

• Added Type column to table ...........................................................................................................................Pin Functions 3

• Added Junction temperature, TJ............................................................................................................................................. 4

• Added and ......................................................Receiving Notication of Documentation Updates Community Resources 19

Changes from Revision J (June 2007) to Revision K Page

• Added section, table, section,Pin Conguration and Functions ESD Ratings Feature Description Device Functional

Modes Application and Implementation Power Supply Recommendations Layout Device, section, section, section,

and Documentation Support Mechanical, Packaging, and Orderable Informationsection, and section .............................. 1