Texas Instruments SN74ALVCH162268DL Bedienungsanleitung


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FEATURES
DESCRIPTION/ORDERING INFORMATION
DGG OR DL PACKAGE
(TOP VIEW)
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OEA
CLKEN1B
2B3
GND
2B2
2B1
V
CC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
V
CC
1B1
1B2
GND
1B3
CLKEN2B
SEL
OEB
CLKENA2
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
CLKENA1
CLK
SN74ALVCH162268
12-BIT TO 24-BIT REGIS
WITH 3-STATE
SCES018L – AUGUST 1995
•Member of the Texas Instruments Widebus™
Family
•Operates From 1.65 V to 3.6 V
•Max t
pd of 4.8 ns at 3.3 V
•±24-mA Output Drive at 3.3 V
• ΩB-Port Outputs Have Equivalent 26- Serie
Resistors, So No External Resistors Are
Required
•Bus Hold on Data Inputs Eliminates the N
for External Pullup/Pulldown Resistors
•Latch-Up Performance Exceeds 250 mA
JESD 17
•ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
This 12-bit to 24-bit registered bus exchanger
designed for 1.65-V to 3.6-V V
CC operation.
The SN74ALVCH162268 is used for applications
which data must be transferred from a narrow
high-speed bus to a wide, lower-frequency bus.
The device provides synchronous data exchange
between the two ports. Data is stored in the inte
registers on the low-to-high transition of the
(CLK) input when the appropriate clock-enable
( CLKEN) inputs are low. The select ( SEL) line
synchronous with CLK and selects 1B or 2B
data for the A outputs.
For data transfer in the A-to-B direction, a two-st
storage register in the A-to-2B path. Proper c
presented synchronously as a 24-bit word on
( OEA, OEB). These control terminals are registere
The B outputs, which are designed to sink up
and undershoot.
ORDERING INFORMATION
TAPACKAGE (1) ORDERABLE PART NUMBER
Tube SN74ALVCH162268DL
SSOP - DL ALVCH162268
Tape and reel SN74ALVCH162268DLR
-40 C to 85 C TSSOP - DGG Tape and reel S° °
VFBGA - GQL SN74ALVCH162268KR
Tape and reel VH2268
VFBGA - ZQL (Pb-free) 74ALVCH162268ZQLR
(1) Package drawings, standard packing quantities, therma
www.ti.com/sc/package.
Please be aware that an important notice concerning
Instruments semiconductor products and disclaimers
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2004, Tex
Products conform to speciî‹Šcations per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
www.ti.com
DESCRIPTION/ORDERING INFORMATION
GQL OR ZQL PACKAGE
(TOP VIEW)
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H
G
F
E
D
C
B
A
21 3 4 65
K
SN74ALVCH162268
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES018L – AUGUST 1995 – REVISED SEPTEMBER 2004
To ensure the high-impedance state during po
possible, and OE should be tied to V
CC through a pullup resistor; the minim
by the current-sinking capability of the driver.
outputs cannot be determined prior to the arrival
Active bus-hold circuitry holds unused or undriven
with the bus-hold circuitry is not recommended.
TERMINAL ASSIGNMENTS
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A2B3 CLKEN1B OEA OE
B2B1 2B2 GND GND
CA2 A1 V
CC VCC 2B7 2B8
DA4 A3 GND GND
EA6 A5 2B11
FA7 A8 1B11
GA9 A10 GND GND
HA11 A12 V
CC VCC 1B7 1B8
J1B1 1B2 GND GND
K1B3 CLKEN2B SEL CLK
2
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FUNCTION TABLES
SN74ALVCH162268
12-BIT TO 24-BIT REGISTERED BUS EXC
WITH 3-STATE OUTPUTS
SCES018L – AUGUST 1995
OUTPUT ENABLE
INPUTS OUTPUTS
CLK OEA OEB A 1B, 2B
↑H H Z Z
↑H L Z Active
↑L H Active Z
↑L L Active Active
A-TO-B STORAGE ( OEB = L)
INPUTS OUTPUTS
CLKENA1 CLKENA2 CLK A 1B
H H X X 1B
0(1) 2B0(1)
L L L L↑(2) X
L L H H↑(2) X
X L L X L↑
X L H X H↑
(1) Output level before the indicated steady-state
established
(2) Two CLK edges are needed to propagate
B-TO-A STORAGE ( OEA = L)
INPUTS OUTPUT
CLKEN1B CLKEN2B CLK SEL 1B 2
H X X H X X A
0(1)
X H X L X X A
0(1)
L L H L X L↑
L L H H X H↑
X L L X L L↑
X L L X H H↑
(1) Output level before the indicated steady-state
were established
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Modell: SN74ALVCH162268DL

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