Texas Instruments CD4050BPWR Bedienungsanleitung


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CD4049UB and CD4050B CMOS Hex Inverting Buffer and Converter
1 Features
• CD4049UB Inverting
• CD4050B Noninverting
• High Sink Current for Driving 2 TTL Loads
• High-to-Low Level Logic Conversion
• 100% Tested for Quiescent Current at 20 V
• Maximum Input Current of 1 µA at 18 V Over Full
Package Temperature Range; 100 nA at 18 V and
25°C
• 5-V, 10-V, and 15-V Parametric Ratings
2 Applications
• CMOS to DTL or TTL Hex Converters
• CMOS Current or DriversSink Source
• CMOS High-to-Low Logic Level Converters
3 Description
The CD4049UB and CD4050B devices are inverting
and noninverting hex buffers, and feature logic-level
conversion using only one supply voltage (VCC). The
input-signal high level (VIH) can exceed the VCC
supply voltage when these devices are used for logic-
level conversions. These devices are intended for use
as CMOS to DTL or TTL converters and can drive
directly two DTL or TTL loads. (VCC = 5 V,
VOL ≤ 0.4 V, and IOL ≥ 3.3 mA.)
Device Information
PART NUMBER(1) PACKAGE BODY SIZE (NOM)
CD4049UBE,
CD4050BE PDIP (16) 6.35 mm × 19.30 mm
CD4049UBD,
CD4050BD SOIC (16) 9.90 mm × 3.91 mm
CD4049UBDW,
CD4050BDW SOIC (16) 10.30 mm × 7.50 mm
CD4049UBNS,
CD4050BNS SO (16) 10.30 mm × 5.30 mm
CD4049UBPW,
CD4050BPW TSSOP (16) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
V
OUT
CC
V
P
SS
N
R
IN
Copyright © 2016,
Texas Instruments Incorporated
1 of 6 Identical Units
Schematic Diagram of CD4049UB
P
N
R
IN
V
OUT
CC
V
P
SS
N
Copyright © 2016, Texas Instruments Incorporated
1 of 6 Identical Units
Schematic Diagram of CD4050B
CD4049UB, CD4050B
SCHS046K – AUGUST 1998 – REVISED JUNE 2020
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics: DC..................................... 5
6.6 Electrical Characteristics: AC......................................9
6.7 Typical Characteristics.............................................. 10
7 Parameter Measurement Information.......................... 11
7.1 Test Circuits...............................................................11
8 Detailed Description......................................................13
8.1 Overview...................................................................13
8.2 Functional Block Diagram......................................... 13
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................14
9 Application and Implementation.................................. 15
9.1 Application Information............................................. 15
9.2 Typical Application.................................................... 15
10 Power Supply Recommendations..............................16
11 Layout........................................................................... 16
11.1 Layout Guidelines................................................... 16
11.2 Layout Example...................................................... 16
12 Device and Documentation Support..........................17
12.1 Documentation Support.......................................... 17
12.2 Related Links.......................................................... 17
12.3 Receiving Notification of Documentation Updates..17
12.4 Support Resources................................................. 17
12.5 Trademarks............................................................. 17
12.6 Electrostatic Discharge Caution..............................17
12.7 Glossary..................................................................17
13 Mechanical, Packaging, and Orderable
Information.................................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (September 2016) to Revision K (June 2020) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated Device Information Table with correct package dimensions................................................................ 1
Changes from Revision I (May 2004) to Revision J (September 2016) Page
• Added table, section, , ESD Ratings Feature Description Device Functional Modes Application and
Implementation Power Supply Recommendations Layout Device and section, section, section,
Documentation Support Mechanical, Packaging, and Orderable Information section, and section................... 1
• Deleted table; see POA at the end of the data sheet.......................................................Ordering Information 1
• Changed Storage temperature minimum value from 65 to –65..........................................................................4
• Changed RθJA values for the CD4049UB device: D (SOIC) from 73 to 81.6, DW (SOIC) from 57 to 81.6, E
(PDIP) from 67 to 49.5, NS (SO) from 64 to 84.3, and PW (TSSOP) from 108 to 108.9................................... 5
• Changed RθJA values for the CD4050B device: D (SOIC) from 73 to 81.6, DW (SOIC) from 57 to 81.2, E
(PDIP) from 67 to 49.7, NS (SO) from 64 to 83.8, and PW (TSSOP) from 108 to 108.4................................... 5
CD4049UB, CD4050B
SCHS046K – AUGUST 1998 – REVISED JUNE 2020 www.ti.com
2Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: CD4049UB CD4050B
5 Pin Configuration and Functions
1VCC 16 NC
2G 15 L
3A 14 F
4H 13 NC
5B 12 K
6I 11 E
7C 10 J
8VSS 9 D
Not to scale
Figure 5-1. CD4049UB D, DW, N, NS, and PW
Packages 16-Pin SOIC, PDIP, SO, and TSSOP Top
View
1VCC 16 NC
2G 15 L
3A 14 F
4H 13 NC
5B 12 K
6I 11 E
7C 10 J
8VSS 9 D
Not to scale
Figure 5-2. CD4050B D, DW, N, NS, and PW
Packages 1G6-Pin SOIC, PDIP, SO, and TSSOP Top
View
Pin Functions: CD4049UB
PIN I/O DESCRIPTION
NAME NO.
A 3 I Input 1
B 5 I Input 2
C 7 I Input 3
D 9 I Input 4
E 11 I Input 5
F 14 I Input 6
G 2 O Inverting output 1. G = A
H 4 O Inverting output 2. H = B
I 6 O Inverting output 3. I = C
J 10 O Inverting output 4. J = D
K 12 O Inverting output 5. K = E
L 15 O Inverting output 6. L = F
NC 13, 16 — No connection
VCC 1 — Power pin
VSS 8 — Negative supply
www.ti.com
CD4049UB, CD4050B
SCHS046K – AUGUST 1998 – REVISED JUNE 2020
Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 3
Product Folder Links: CD4049UB CD4050B


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Modell: CD4050BPWR

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