Microchip TC1044S Bedienungsanleitung

Microchip Nicht kategorisiert TC1044S

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TC1044S
TC1044S-12 9/16/96
EVALUATION
KIT
AVAILABLE
© 2001 Microchip Technology Inc. DS21348A
Charge Pump DC-TO-DC Voltage Converter
FEATURES
■Converts +5V Logic Supply to ±5V System
■Wide Input Voltage Range .................... 1.5V to 12V
■Ecient Voltage Conversion ......................... 99.9%
■Excellent Power Eciency ............................... 98%
■Low Power Consumption ............ 80µA @ V IN = 5V
■Low Cost and Easy to Use
— Only Two External Capacitors Required
■RS-232 Negative Power Supply
■Available in 8-Pin Small Outline (SOIC) and 8-Pin
Plastic DIP Packages
■Improved ESD Protection ..................... Up to 10kV
■No External Diode Required for High Voltage
Operation
■Frequency Boost Raises F OSC to 45kHz
GENERAL DESCRIPTION
The TC1044S is a pin-compatible upgrade to the Indus-
try standard TC7660 charge pump voltage converter. It
converts a +1.5V to +12V input to a corresponding –1.5V
to –12V output using only two low cost capacitors, eliminat-
ing inductors and their associated cost, size and EMI.
Added features include an extended supply range to 12V,
and a frequency boost pin for higher operating frequency,
allowing the use of smaller external capacitors.
The on-board oscillator operates at a nominal frequency
of 10kHz. Frequency is increased to 45kHz when pin 1 is
connected to V+. Operation below 10kHz (for lower supply
current applications) is possible by connecting an external
capacitor from OSC to ground (with pin 1 open).
The TC1044S is available in both 8-pin DIP and
8-pin small outline (SOIC) packages in commercial and
extended temperature ranges.
FUNCTIONAL BLOCK DIAGRAM
TC1044S
GND
INTERNAL
VOLTAGE
REGULATOR
RC
OSCILLATOR
VOLTAGE–
LEVEL
TRANSLATOR
2
V+CAP +
8 2
7
6
OSC
LV
3
LOGIC
NETWORK
VOUT
5
CAP –
4
1
BOOST
ORDERING INFORMATION
Part No. Package Temp. Range
TC1044SCOA 8-Pin SOIC 0° °C to +70 C
TC1044SCPA 8-Pin Plastic DIP 0° °C to +70 C
TC1044SEOA 8-Pin SOIC – 40° °C to +85 C
TC1044SEPA 8-Pin Plastic DIP – 40° °C to +85 C
TC1044SIJA 8-Pin CerDIP – 25° °C to +85 C
TC1044SMJA 8-Pin CerDIP – 55° °C to +125 C
TC7660EV Charge Pump Family Evaluation Kit
PIN CONFIGURATION (DIP AND SOIC)
1
2
3
4
8
7
6
5
TC1044SCPA
TC1044SEPA
TC1044SIJA
TC1044SMJA
BOOST
CAP+
GND
CAP–VOUT
LOW
VOLTAGE (LV)
OSC
+
V1
2
3
4
8
7
6
5
TC1044SCOA
TC1044SEOA
BOOST
CAP +
GND
CAP –VOUT
LOW
VOLTAGE (LV)
OSC
+
V
TC1044S-12 9/16/96
TC1044S
Charge Pump DC-TO-DC Voltage Converter
2© 2001 Microchip Technology Inc. DS21348A
Package Power Dissipation (TA ≤ 70°C) (Note 2)
8-Pin CerDIP ..................................................800mW
8-Pin Plastic DIP .............................................730mW
8-Pin SOIC .....................................................470mW
Operating Temperature Range
C Sux .................................................. 0°C to +70°C
I Sux ............................................... – 25°C to +85°C
E Sux ............................................. – 40°C to +85°C
M Sux ........................................... – 55°C to +125°C
Storage Temperature Range ................ – 65°C to +150°C
ELECTRICAL CHARACTERISTICS: TA = +25°C, V+ = 5V, COSC = 0, Test Circuit (Figure 1), unless otherwise
indicated.
Symbol Parameter Test Conditions Min Typ Max Unit
I+Supply Current RL = ∞— 80 160 µA
0°C < TA < +70°C — — 180
– 40 C < T°A < +85°C — — 180
– 55 C < T°A < +125°C — — 200
I+Supply Current 0°C < TA < +70° µC — — 300 A
(Boost Pin = V+) – 40°C < TA < +85°C — — 350
– 55 C < T°A < +125°C — — 400
V+
H2 Supply Voltage Range, High Min ≤ TA ≤ Max, 3 — 12 V
RL = 10 k , LV OpenΩ
V+
L2 Supply Voltage Range, Low Min ≤ TA ≤ Max, 1.5 — 3.5 V
RL = 10 kΩ, LV to GND
ROUT Output Source Resistance IOUT = 20mA — 60 100 Ω
IOUT = 20mA, 0°≤C TA ≤ +70°C — 70 120
IOUT = 20mA, –40°≤C TA ≤ +85°C — 70 120
IOUT = 20mA, –55°≤C TA ≤ +125°C — 105 150
V+ = 2V, IOUT = 3 mA, LV to GND
0 C °≤ TA ≤ +70°C — — 250 Ω
– 55 C T°≤A +125≤°C — — 400
FOSC Oscillator Frequency Pin 7 open; Pin 1 open or GND — 10 — kHz
Boost Pin = V+— 45 —
PEFF Power Eciency RL = 5 kΩ; Boost Pin Open 96 98 — %
TMIN < TA < T
MAX ; Boost Pin Open 95 97 —
Boost Pin = V+— 88 —
VOUT EFF Voltage Conversion Eciency RL = ∞99 99.9 — %
ZOSC Oscillator Impedance V+ = 2V — 1 — MΩ
V+ = 5V — 100 — kΩ
NOTES: 1. Connecting any input terminal to voltages greater than V
+ or less than GND may cause destructive latch-up. It is recommended that no
inputs from sources operating from external supplies be applied prior to "power up" of the TC1044S.
2. Derate linearly above 50° °C by 5.5mW/ C.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage ......................................................... +13V
LV, Boost and OSC Inputs
Voltage (Note 1) ......................... – 0.3V to (V++ 0.3V)
for V+
< 5.5V
(V+ – 5.5V) to (V++ 0.3V)
for V+ > 5.5V
Current Into LV (Note 1) ...................... 20µA for V+ > 3.5V
Output Short Duration (VSUPPLY 5.5V) ......... Continuous≤
Lead Temperature (Soldering, 10 sec) ................. +300°C
*Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static elds. Stresses above those
listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device
at these or any other conditions above those indicated in the operation sections of the specications is not implied. Exposure to absolute maximum rating
conditions for extended periods may aect device reliability.
3
TC1044S
Charge Pump DC-TO-DC Voltage Converter
TC1044S-12 9/16/96
© 2001 Microchip Technology Inc. DS21348A
Circuit Description
The TC1044S contains all the necessary circuitry to
implement a voltage inverter, with the exception of two
external capacitors, which may be inexpensive 10 F polar-µ
ized electrolytic capacitors. Operation is best understood by
considering Figure 2, which shows an idealized voltage
inverter. Capacitor C1 is charged to a voltage, V+, for the half
cycle when switches S1 and S3 are closed. (Note: Switches
S2 and S4 are open during this half cycle.) During the second
half cycle of operation, switches S2 and S4 are closed, with
S1 and S3 open, thereby shifting capacitor C1 negatively by
V+ volts. Charge is then transferred from C1 to C2, such that
the voltage on C2 is exactly V+, assuming ideal switches and
no load on C2.
The four switches in Figure 2 are MOS power switches;
S1 is a P-channel device, and S2, S3 and S4 are N-channel
devices. The main diculty with this approach is that in
integrating the switches, the substrates of S3 and S4 must
always remain reverse-biased with respect to their sources,
but not so much as to degrade their ON resistances. In
addition, at circuit start-up, and under output short circuit
conditions (VOUT = V+), the output voltage must be sensed
and the substrate bias adjusted accordingly. Failure to
accomplish this will result in high power losses and probable
device latch-up.
This problem is eliminated in the TC1044S by a logic
network which senses the output voltage (VOUT ) together
with the level translators, and switches the substrates of
S3 and S4 to the correct level to maintain necessary reverse
bias.
Figure 2. Idealized Charge Pump Inverter
V+
GND S3
S1S2
S4
C2
VOUT = V–IN
C1
The voltage regulator portion of the TC1044S is an
integral part of the anti-latch-up circuitry. Its inherent voltage
drop can, however, degrade operation at low voltages. To
improve low-voltage operation, the “LV” pin should be
connected to GND, disabling the regulator. For supply
voltages greater than 3.5V, the LV terminal must be left
open to ensure latch-up-proof operation and prevent device
damage.
Theoretical Power Eciency
Considerations
In theory, a capacitive charge pump can approach
100% eciency if certain conditions are met:
(1) The drive circuitry consumes minimal power.
(2) The output switches have extremely low ON
resistance and virtually no oset.
(3) The impedances of the pump and reservoir
capacitors are negligible at the pump frequency.
The TC1044S approaches these conditions for nega-
tive voltage multiplication if large values of C1 and C2 are
used. Energy is lost only in the transfer of charge
between capacitors if a change in voltage occurs. The
energy lost is dened by:
E = 1/2 C1 (V12 – V22)
V1 and V2 are the voltages on C1 during the pump and
transfer cycles. If the impedances of C1 and C2 are relatively
high at the pump frequency (refer to Figure 2) compared to
the value of RL, there will be a substantial dierence in
voltages V1 and V2. Therefore, it is desirable not only to
make C2 as large as possible to eliminate output voltage
ripple, but also to employ a correspondingly large value for
C1 in order to achieve maximum eciency of operation.
1
2
3
4
8
7
6
5
TC1044S
+
V+
(+5V)
VOUT
C
1
1 Fµ
COSC
*
+
C2
10 Fµ
IL
RL
IS
V+
NOTE: For large values of COSC (>1000pF), the values
of C1 and C2 should be increased to 100 F.µ
Figure 1. TC1044S Test Circuit

Produktspezifikationen

Marke: Microchip
Kategorie: Nicht kategorisiert
Modell: TC1044S

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