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Section 35. Ethernet Controller

This section of the manual contains the following major topics:

35.1 Introduction .............................................................................................................. 35-2

35.2 Ethernet Controller Overview .................................................................................. 35-3

35.3 Status and Control Registers................................................................................... 35-4

35.4 Operation...............................................................................................................35-43

35.5 Ethernet Interrupts................................................................................................. 35-82

35.6 Operation in Power-Saving and Debug Modes ..................................................... 35-87

35.7 Effects of Various Resets....................................................................................... 35-90

35.8 I/O Pin Control ....................................................................................................... 35-91

35.9 Related Application Notes ..................................................................................... 35-92

35.10 Revision History..................................................................................................... 35-93

PIC32 Family Reference Manual

35.1 INTRODUCTION

The Ethernet Controller is a bus master module that interfaces with an off-chip PHY to implement

a complete Ethernet node in an embedded system.

The following are key features of the Ethernet Controller module:

• Supports 10/100 Mbps data transfer rates (see the Caution note in 35.4 “Operation”)

• Supports the full-duplex and half-duplex operation

• Supports the Reduced Media Independent Interface (RMII) and Media Independent

Interface (MII) PHY interface

• Supports the MII Management (MIIM) PHY Management interface

• Supports manual and automatic Flow Control

• Supports Auto-MDIX and enabled PHYs

• RAM descriptor based Direct Memory Access (DMA) operation for receive and transmit

path

• Fully configurable interrupts

• Configurable receive packet filtering

- Cyclic Redundancy Check (CRC)

- 64-byte pattern match

- Broadcast, multicast, and unicast packets

- Magic Packet™

- 64-bit Hash table

- Runt packet

• Supports Packet Payload Checksum calculation

• Supports various hardware statistics counters

Note: This family reference manual section is meant to serve as a complement to device

data sheets. Depending on the device variant, this manual section may not apply to

all PIC32 devices.

Please consult the note at the beginning of the “Ethernet Controller” chapter in

the current device data sheet to check whether this document supports the device

you are using.

Device data sheets and family reference manual sections are available for

download from the Microchip Worldwide Web site at: http://www.microchip.com

Note: To avoid cache coherency problems on devices with L1 cache, it is recommended

to access the Ethernet buffers from the KSEG1 segment.

Section 35. Ethernet Controller

35.2 ETHERNET CONTROLLER OVERVIEW

The Ethernet Controller provides the modules needed to implement a 10/100 Mbps Ethernet

node uses an external PHY chip. To offload the CPU from a moving packet data to and from the

module, the internal descriptor based DMA engines are included in the controller.

The Ethernet Controller consists of the following modules:

• Media Access Control (MAC) block: This module implements the MAC functions of the

IEEE 802.3

Specification

• Flow Control block: This module controls the transmission of PAUSE frames. Reception of

PAUSE frames is handled within the MAC

• RX Filter (RXF) block: This module performs filtering on every receive packet to determ ine

whether each packet to be accepted or rejected

• TX DMA/TX Buffer Management (BM) Engine: The TX DMA and TX BM engines perform

data transfers from the system memory (using descriptor tables) to the MAC transmit

interface

• RX DMA/RX BM Engine: The RX DMA and RX BM engines transfer receive packets from

the MAC to the system memory (using descriptor tables)

Figure 35-1 illustrates the block d iagram of the Ethernet Controller.

Figure 35-1: Ethernet Controller Block Diagram

Note: Refer to the “Ethernet Theory of Operation” (DS01120) for more information on the

Ethernet operation and the IEEE 802.3 Specification (www.ieee.org).

TX Bus

Master

System BUS

RX Bus

Master

TX DMA

TX Flow Control

Host I/F

RX DMA

RX Filter

Checksum

MAC External

PHY

MII/RMII

I/F

MIIM

MAC Control

and

Configuration

Registers

TX Function

RX Function

DMA

Control

Registers

Fast Peripheral Bus

Ethernet Controller

RX Flow

Control

Ethernet DMA

RX BM

TX BM

FIFO

PIC32 Family Reference Manual

35.3 STATUS AND CONTROL REGISTERS

The Ethernet Controller module consists of the following Special Function Registers (SFRs):

Controller and DMA Engine Configuration/Status Registers:

•ETHCON1: Ethernet Controller Control 1 Register

•ETHCON2: Ethernet Controller Control 2 Register

•ETHTXST: Ethernet Controller TX Packet Descriptor Start Address Register

•ETHRXST: Ethernet Controller RX Packet Descriptor Start Address Register

•ETHIEN: Ethernet Controller Interrupt Enable Register

•ETHIRQ: Ethernet Controller Interrupt Request Register

•ETHSTAT: Ethernet Controller Status Register

RX Filtering Configuration Registers:

•ETHRXFC: Ethernet Controller Receive Filter Configuration Register

•ETHHT0: Ethernet Controller Hash Table 0 Register

•ETHHT1: Ethernet Controller Hash Table 1 Register

•ETHPMM0: Ethernet Controller Pattern Match Mask 0 Register

•ETHPMM1: Ethernet Controller Pattern Match Mask 1 Register

•ETHPMCS: Ethernet Controller Pattern Match Checksum Register

•ETHPMO: Ethernet Controller Pattern Match Offset Register

Flow Control Configuring Register:

•ETHRXWM: Ethernet Controller Receive Watermarks Register

Ethernet Statistics Registers:

•ETHRXOVFLOW: Ethernet Controller Receive Overflow Statistics Register

•ETHFRMTXOK: Ethernet Controller Frames Transmitted Okay Statistics Register

•ETHSCOLFRM: Ethernet Controller Single Collision Frames Statistics Register

•ETHMCOLFRM: Ethernet Controller Multiple Collision Frames Statistics Register

•ETHFRMRXOK: Ethernet Controller Frames Received Okay Statistics Register

•ETHFCSERR: Ethernet Controller Frame Check Sequence Error Statistics Register

•ETHALGNERR: Ethernet Controller Alignment Errors Statistics Register

MAC Configuration Registers:

•EMAC1CFG1: Ethernet Controller MAC Configuration 1 Register

•EMAC1CFG2: Ethernet Controller MAC Configuration 2 Register

•EMAC1IPGT: Ethernet Controller MAC Back-to-Back Interpacket Gap Register

•EMAC1IPGR: Ethernet Controller MAC Non-Back-to-Back Interpacket Gap Register

•EMAC1CLRT: Ethernet Controller MAC Collision Window/Retry Limit Register

•EMAC1MAXF: Ethernet Controller MAC Maximum Frame Length Register

•EMAC1SUPP: Ethernet Controller MAC PHY Support Register

•EMAC1TEST: Ethernet Controller MAC Test Register

•EMAC1SA0: Ethernet Controller MAC Address 0 Register

•EMAC1SA1: Ethernet Controller MAC Address 1 Register

•EMAC1SA2: Ethernet Controller MAC Address 2 Register

MII Management Registers:

•EMAC1MCFG: Ethernet Controller MAC MII Management Configuration Register

•EMAC1MCMD: Ethernet Controller MAC MII Management Command Register

•EMAC1MADR: Ethernet Controller MAC MII Management Address Register

•EMAC1MWTD: Ethernet Controller MAC MII Management Write Data Register

•EMAC1MRDD: Ethernet Controller MAC MII Management Read Data Register

•EMAC1MIND: Ethernet Controller MAC MII Management Indicators Register

Table 35-1 provides a summary of the Ethernet Controller registers. Corresponding registers appear after the su

detailed description of each register.

Table 35-1: Ethernet Controller Register Summary

Name

(1)

Bit

Range Bit 31/15 Bit 30/14 Bit 29/13 Bit 28/12 Bit 27/11 Bit 26/10 Bit 25/9 Bit 24/8 Bit 23/7 Bit 22/6 Bit 21/5 Bit Bit 20/4

ETHCON1 31:16 PTV<15:8> PTV<7:0>

15:0 ON — — — — — — —SIDL TXRTS RXEN AUTOFC MANFC

ETHCON2 31:16 — — — — — — — — — — — —

15:0 — — — — — —RXBUFSZ<6:4> RXBUFSZ<3:0>

ETHTXST 31:16 TXSTADDR<31:24> TXSTADDR<23:

15:0 TXSTADDR<15:8> TXSTADDR<7:2>

ETHRXST 31:16 RXSTADDR<31:24> RXSTADDR<23:

15:0 RXSTADDR<15:8> RXSTADDR<7:2>

ETHHT0 31:16 HT<31:24> HT<23:16>

15:0 HT<15:8> HT<7:0>

ETHHT1 31:16 HT<63:56> HT<55:48>

15:0 HT<47:40> HT<39:32>

ETHPMM0 31:16 PMM<31: 24> PMM<23:16>

15:0 PMM<15:8> PMM<7:0>

ETHPMM1 31:16 PMM<63:56> PMM<55:48>

15:0 PMM<47:40> PMM<39:32>

ETHPMCS 31:16 — — — — — — — — — — — —

15:0 PMCS<15:8> PMCS<7:0>

ETHPMO 31:16 — — — — — — — — — — — —

15:0 PMO<15:8> PMO<7:0>

ETHRXFC

31:16 — — — — — — — — — — — —

15:0 HTEN MPEN — NOTPM PMMODE<3:0> CRC

ERREN CRCOKEN RUNT

ERREN RUNTEN U

ETHRXWM 31:16 — — — — — — — — RXFWM<7:0

15:0 — — — — — — — — RXEWM<7:0

ETHIEN

31:16 — — — — — — — — — — — —

15:0 — — — —TXBUSEIE RXBUSEIE EW

MARKIE

DONEIE

PKT

PENDIE RXACTIE — DO

ETHIRQ

31:16 — — — — — — — — — — — —

15:0 — — — — —TXBUSE RXBUSE EWMARK RXACTFWMARK RXDONE PKTPEND TXD

ETHSTAT 31:16 — — — — — — — — BUFCNT<7:0

15:0 — — — — — — — — — —ETHBUSY TXBUSY RXBUSY

ETH

RXOVFLOW

31:16 — — —

15:0 RXOVFLWCNT<15:8> RXOVFLWCNT<

Legend: — = unimplemented, read as ‘0’.

Note 1: With the exception of the ETHSTAT register, all registers have an associated Clear, Set, and Invert register at an offset of 0x4, 0x8, and 0xC bytes, respectively. These registers

CLR, SET, or INV appended to the end of the register name (e.g., ETHCON1CLR). Writing a ‘1’ to any bit position in these registers will clear, set, or invert valid bits in the as

these registers should be ignored.

ETH

FRMTXOK

31:16 — — — — — — — — — — — —

15:0 FRMTXOKCNT<15:0>

ETH

SCOLFRM

31:16 — — — — — — — — — — — —

15:0 SCOLFRMCNT<15:0>

ETH

MCOLFRM

31:16 — — — — — — — — — — — —

15:0 MCOLFRMCNT<15:0>

ETH

FRMRXOK

31:16 — — — — — — — — — — — —

15:0 FRMRXOKCNT<15:0>

ETH

FCSERR

31:16 — — — — — — — — — — — —

15:0 FCSERRCNT<15:0>

ETH

ALGNERR

31:16 — — — — — — — — — — — —

15:0 ALGNERRCNT<15:0>

EMAC1CFG1

31:16 — — — — — — — — — — — —

15:0 SOFT

RESET

SIM

RESET — — RESET

RMCS

RESET

RFUN

RESET

TMCS

RESET

TFUN — — — LOOP

BACK TXP

EMAC1CFG2

31:16 — — — — — — — — — — — —

15:0 — EXCESS

DFR

BPNO

BKOFF

BKOFF — — LONGPRE PUREPRE AUTOPAD VLANPAD PAD

ENABLE

CRC

ENABLE

EMAC1IPGT 31:16 — — — — — — — — — — — —

15:0 — — — — — — — — — B2BIPK

EMAC1IPGR 31:16 — — — — — — — — — — — —

15:0 NB2BIPKTGP1<6:0> NB2BIPK— —

EMAC1CLRT 31:16 — — — — — — — — — — — —

15:0 — — — — — —CWINDOW<5:0>

EMAC1MAXF 31:16 — — — — — — — — — — — —

15:0 MACMAXF<15:0>

EMAC1SUPP

31:16 — — — — — — — — — — — —

15:0 — — — — — —RESETRMII SPEED

RMII — — — —

EMAC1TEST

31:16 — — — — — — — — — — — —

15:0 — — — — — — — — — — — —

EMAC1MCFG

31:16 — — — — — — — — — — — —

15:0 RESET

MGMT — — — — — — — — — CLKSEL<3:

EMAC1MCMD 31:16 — — — — — — — — — — — —

15:0 — — — — — — — — — — — —

EMAC1MADR 31:16 — — — — — — — — — — — —

15:0 — — — PHYADDR<4:0> — — —

Table 35-1: Ethernet Controller Register Summary (Continued)

Name

(1)

Bit

Range Bit 31/15 Bit 30/14 Bit 29/13 Bit 28/12 Bit 27/11 Bit 26/10 Bit 25/9 Bit 24/8 Bit 23/7 Bit 22/6 Bit 21/5 Bit 20/4 Bit

Legend: — = unimplemented, read as ‘0’.

Note 1: With the exception of the ETHSTAT register, all registers have an associated Clear, Set, and Invert register at an offset of 0x4, 0x8, and 0xC bytes, respectively.

CLR, SET, or INV appended to the end of the register name (e.g., ETHCON1CLR). Writing a ‘1’ to any bit position in these registers will clear, set, or invert valid

these registers should be ignored.

EMAC1MWTD 31:16 — — — — — — — — — — — —

15:0 MWTD<15:0>

EMAC1MRDD 31:16 — — — — — — — — — — — —

15:0 MRDD<15:0>

EMAC1MIND 31:16 — — — — — — — — — — — —

15:0 — — — — — — — — — — — — LIN

EMAC1SA0 31:16 — — — — — — — — — — — —

15:0 STNADDR6<7:0> STNADDR5<7

EMAC1SA1 31:16 — — — — — — — — — — — —

15:0 STNADDR4<7:0> STNADDR3<7

EMAC1SA2 31:16 — — — — — — — — — — — —

15:0 STNADDR2<7:0> STNADDR1<7

Table 35-1: Ethernet Controller Register Summary (Continued)

Name

(1)

Bit

Range Bit 31/15 Bit 30/14 Bit 29/13 Bit 28/12 Bit 27/11 Bit 26/10 Bit 25/9 Bit 24/8 Bit 23/7 Bit 22/6 Bit 21/5 Bit 20/4 Bit

Legend: — = unimplemented, read as ‘0’.

Note 1: With the exception of the ETHSTAT register, all registers have an associated Clear, Set, and Invert register at an offset of 0x4, 0x8, and 0xC bytes, respectively.

CLR, SET, or INV appended to the end of the register name (e.g., ETHCON1CLR). Writing a ‘1’ to any bit position in these registers will clear, set, or invert valid

these registers should be ignored.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PTV<15:8>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PTV<7:0>

15:8

R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0

ON — SIDL — — — TXRTS RXEN

(1)

7:0

R/W-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0

AUTOFC — — MANFC — — — BUFCDEC

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 PTV<15:0>: PAUSE Timer Value bits

This register should be written only when the RXEN bit (ETHCON1<8>) is not set. These bits are only used

for Flow Control operations.

bit 15 ON: Ethernet ON bit

1 = Ethernet module is enabled

0 = Ethernet module is disabled

bit 14 Read as ‘Unimplemented: 0’

bit 13 SIDL: Ethernet Stop in Idle Mode bit

1 = Ethernet module transfers are suspended during Idle mode

0 = Ethernet module transfers continue during Idle mode

bit 12-10 Read as ‘Unimplemented: 0’

bit 9 TXRTS: Transmit Request to Send bit

1 = Activate the transmit logic and send the packets defined in the TX Ethernet Descriptor Table (EDT)

0 = Stop transmit (when cleared by software) or transmit done (when cleared by hardware)

After the bit is written with a ‘1 0’, it will clear to ‘ ’ whenever the transmit logic has finished transmitting the

requested packets in the EDT. If ‘0’ is written by the CPU, the transmit logic finishes the current packet’s

transmission, and then stops any further transmission.

This bit only affects TX operations.

bit 8 RXEN: Receive Enable bit

(1)

1 = Enable RX logic, packets are received and stored in the RX buffer as controlled by the filter configuration

0 = Disable RX logic, no packets are received in the RX buffer

This bit only affects RX operations.

bit 7 AUTOFC: Automatic Flow Control bit

1 = Automatic Flow Control is enabled

0 = Automatic Flow Control is disabled

Setting this bit will enable the automatic Flow Control. If set, the full and empty watermarks are used to

automatically enable and disable the Flow Control. When the number of received buffers BUFCNT<7:0> bits

(ETHSTAT<23:16>) rises to the full watermark, Flow Control is automatically enabled. When the BUFCNT

falls to the empty watermark, Flow Control is automatically disabled.

This bit is only used for Flow Control operations, and affects both TX and RX operations.

bit 6-5 Unimplemented: Read as ‘0’

Note 1: It is not recommended to clear the RXEN bit, and then make changes to any RX related field/register. The

Ethernet Controller must be reinitialized (ON cleared to ‘0’), and then the RX changes applied.

Section 35. Ethernet Controller

bit 4 MANFC: Manual Flow Control bit

1 = Manual Flow Control is enabled

0 = Manual Flow Control is disabled

Setting this bit will enable the manual Flow Control. If set, the Flow Control logic will send a PAUSE frame

using the PTV<15:0> bits (ETHCON1<31:16>). It will then resend a PAUSE frame every 128 * PTV<15:0>/2

TX clock cycles until the bit is cleared.

For 10 Mbps operation, the TX clock runs at 2.5 MHz. For 100 Mbps operation, the TX clock runs at

25 MHz.

When this bit is cleared, the Flow Control logic will automatically send a PAUSE frame with a 0x0000 PAUSE

timer value to disable Flow Control.

This bit is only used for Flow Control operations, and affects both TX and RX operations.

bit 3-1 Unimplemented: Read as ‘0’

bit 0 BUFCDEC: Descriptor Buffer Count Decrement bit

The BUFCDEC bit is a write-1 bit that reads out ‘0’. When written with ‘1’, the Descriptor Buffer Counter,

BUFCNT, will decrement by one. If the BUFCNT counter is incremented by the RX logic at the same time

that this bit is written, the BUFCNT value will remain unchanged. Writing ‘0’ will have no effect.

This bit is only used for RX operations.

Note 1: It is not recommended to clear the RXEN bit, and then make changes to any RX related field/register. The

Ethernet Controller must be reinitialized (ON cleared to ‘0’), and then the RX changes applied.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — RXBUFSZ<6:4>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0

RXBUFSZ<3:0> — — — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-11 Read as ‘Unimplemented: 0’

bit 10-4 RXBUFSZ<6:0>: RX Data Buffer Size for all RX Descriptors (in 16-byte increments) bits

0x7F = RX data Buffer size for descriptors is 2032 bytes

•

0x60 = RX data Buffer size for descriptors is 1536 bytes

•

0x03 = RX data Buffer size for descriptors is 48 bytes

0x02 = RX data Buffer size for descriptors is 32 bytes

0x01 = RX data Buffer size for descriptors is 16 bytes

0x00 = Reserved

bit 3-0 Read as ‘Unimplemented: 0’

Note 1: This register is only used for RX operations.

2: The bits in this register may be changed only when the RXEN bit (ETHCON1<8>) = 0.

Section 35. Ethernet Controller

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TXSTADDR<31:24>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TXSTADDR<23:16>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TXSTADDR<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0

TXSTADDR<7:2> — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-2 TXSTADDR<31:2>: Starting Address of First Transmit Descriptor bits

This register should not be written while any transmit, receive or DMA operations are in progress.

This address must be 4-byte aligned (i.e., bits 1-0 must be ‘00’).

bit 1-0 Unimplemented: Read as ‘0’

Note 1: This register is only used for TX operations.

2: This register will be updated by hardware with the last descriptor used by the last successfully transmitted

packet.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RXSTADDR<31:24>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RXSTADDR<23:16>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RXSTADDR<15:8>

7:0

R/W-0 R/W-0 U-0 U-0R/W-0 R/W-0 R/W-0 R/W-0

RXSTADDR<7:2> — —

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-2 RXSTADDR<31:2>: Starting Address of First Receive Descriptor bits

This register should not be written while any transmit, receive or DMA operations are in progress.

This address must be 4-byte aligned (i.e., bits 1-0 must be ‘00’).

bit 1-0 Unimplemented: Read as ‘0’

Note 1: This register is only used for RX operations.

2: This register will be updated by hardware with the last descriptor used by the last successfully transmitted

packet.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

HT<31:24>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

HT<23:16>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

HT<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

HT<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 HT<31:0>: Hash Table Bytes 0-3 bits

Note 1: This register is only used for RX operations.

2: The bits in this register may be changed only when the RXEN bit (ETHCON1<8>) = 0, or the HTEN bit

(ETHRXFC<15>) = 0.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0

HT<63:56>

23:16

R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0

HT<55:48>

15:8

R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0

HT<47:40>

7:0

R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0 R/W-0 R/W-0

HT<39:32>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 HT<63:32>: Hash Table Bytes 4-7 bits

Note 1: This register is only used for RX operations.

2: The bits in this register may be changed only when the RXEN bit (ETHCON1<8>) = 0, or the HTEN bit

(ETHRXFC<15>) .= 0

Section 35. Ethernet Controller

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PMM<31:24>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PMM<23:16>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PMM<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PMM<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Pattern Match Mask 3 bitsPMM<31:24>:

bit 23-16 Pattern Match Mask 2 bitsPMM<23:16>:

bit 15-8 PMM<15:8>: Pattern Match Mask 1 bits

bit 7-0 PMM<7:0>: Pattern Match Mask 0 bits

Note 1: This register is only used for RX operations.

2: The bits in this register may be changed only when the RXEN bit (ETHCON1<8>) = 0, or the PMMODE

<3:0>bits (ETHRXFC<11:8>) = 0.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

PMM<63:56>

23:16

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

PMM<55:48>

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

PMM<47:40>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

PMM<39:32>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Pattern Match Mask 7 bitsPMM<63:56>:

bit 23-16 Pattern Match Mask 6 bitsPMM<55:48>:

bit 15-8 Pattern Match Mask 5 bitsPMM<47:40>:

bit 7-0 Pattern Match Mask 4 bitsPMM<39:32>:

Note 1: This register is only used for RX operations.

2: The bits in this register may be changed only when the RXEN bit (ETHCON1<8>) = 0, or the

PMMODE<3:0> bits (ETHRXFC<11:8>) = 0.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PMCS<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PMCS<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Read as ‘Unimplemented: 0’

bit 15-8 PMCS<15:8>: Pattern Match Checksum 1 bits

bit 7-0 PMCS<7:0>: Pattern Match Checksum 0 bits

Note 1: This register is only used for RX operations.

2: The bits in this register may be changed only when the RXEN bit (ETHCON1<8>) = 0, or the PMMODE

<3:0>bits (ETHRXFC<11:8>) = 0.

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

PMO<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0R/W-0 R/W-0

PMO<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Read as ‘Unimplemented: 0’

bit 15-0 PMO<15:0>: Pattern Match Offset 1 bits

Note 1: This register is only used for RX operations.

2: The bits in this register may be changed only when the RXEN bit (ETHCON1<8>) = 0, or the PMMODE

<3:0>bits (ETHRXFC<11:8>) = 0.

Section 35. Ethernet Controller

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0

— TXBUSE

(1)

RXBUSE

(2)

— — — EWMARK

(2)

FWMARK

(2)

7:0

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

RXDONE

(2)

PKTPEND

(2)

RXACT

(2)

— TXDONE

(1)

TXABORT

(1)

RXBUFNA

(2)

RXOVFLW

(2)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-15 Unimplemented: Read as ‘0’

bit 14 TXBUSE: Transmit BVCI Bus Error Interrupt bit

(1)

1 = BVCI bus error occurred

0 = No BVCI error occurred

This bit is set when the TX DMA encounters a BVCI bus error during a system memory access. It is cleared

by either a Reset or CPU write of a ‘1’ to the CLR register.

bit 13 RXBUSE: Receive BVCI Bus Error Interrupt bit

(2)

1 = BVCI bus error occurred

0 = No BVC error occurred

This bit is set when the RX DMA encounters a BVCI bus error during a system memory access. It is cleared

by either a Reset or CPU write of a ‘1’ to the CLR register.

bit 12-10 Unimplemented: Read as ‘0’

bit 9 EWMARK: Empty Watermark Interrupt bit

(2)

1 = Empty Watermark pointer reached

0 = No interrupt pending

This bit is set when the RX Descriptor Buffer Count is less than or equal to the value in the RXEWM

<7:0>bits (ETHRXWM<7:0>). It is cleared by the BUFCNT<7:0> bits (ETHSTAT<23:16>) being

incremented by hardware. Writing a ‘0’ or a ‘1’ has no effect.

bit 8 FWMARK: Full Watermark Interrupt bit

(2)

1 = Full Watermark pointer reached

0 = No interrupt pending

This bit is set when the RX Descriptor Buffer Count is greater than or equal to the value in the

RXFWM<7:0> bits (ETHRXWM<23:16>). It is cleared by writing the BUFCDEC bit (ETHCON1<0>) to dec-

rement the BUFCNT counter. Writing a ‘0’ or a ‘1’ has no effect.

bit 7 RXDONE: Receive Done Interrupt bit

(2)

1 = RX packet was successfully received

0 = No interrupt pending

This bit is set whenever a RX packet is successfully received. It is cleared by either a Reset or CPU write of

a ‘1’ to the CLR register.

Note 1: This bit is only used for TX operations.

2: This bit is only used for RX operations.

Note: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or

clearing any bits in this register should be done only for debug/test purposes.

PIC32 Family Reference Manual

bit 6 TXBUSY: Transmit Busy bit

(2, 5)

1 = TX logic is receiving data

0 = TX logic is idle

This bit indicates that a packet is currently being transmitted. A change in this status bit is not necessarily

reflected by the TXDONE interrupt, as TX packets may be aborted or rejected by the MAC.

bit 5 RXBUSY: Receive Busy bit

(3, 5)

1 = RX logic is receiving data

0 = RX logic is idle

This bit indicates that a packet is currently being received. A change in this status bit is not necessarily

reflected by the RXDONE interrupt, as RX packets may be aborted or rejected by the RX filter.

bit 4-0 Unimplemented: Read as ‘0’

Note 1: These bits are only used for RX operations.

2: This bit is only affected by TX operations.

3: This bit is only affected by RX operations.

4: This bit will be set when the ON bit (ETHCON1<15>) = 1.

5: This bit will be cleared when the ON bit (ETHCON1<15>) = 0.

PIC32 Family Reference Manual

Bit

Range

Bit

31/23/15/7

Bit

30/22/14/6

Bit

29/21/13/5

Bit

28/20/12/4

Bit

27/19/11/3

Bit

26/18/10/2

Bit

25/17/9/1

Bit

24/16/8/0

31:24

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

23:16

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

15:8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ALGNERRCNT<15:8>

7:0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ALGNERRCNT<7:0>

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 Alignment Error Count bitsALGNERRCNT<15:0>:

Increment count for frames with alignment errors. Note that an alignment error is a frame that has an FCS

error and the frame length in bits is not an integral multiple of eight bits (also known as, dribble nibble).

Note 1: This register is only used for RX operations.

2: This register is automatically cleared by hardware after a read operation, unless the byte enables for

bytes 0/1 are ‘0’.

3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or

clearing any bits in this register should only be done for debug/test purposes.

Produktspezifikationen

Marke:	Microchip
Kategorie:	Nicht kategorisiert
Modell:	PIC32MX695F512H

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