Microchip PIC32MX150F256H Bedienungsanleitung

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© 2007-2012 Microchip Technology Inc. DS61113E-page 2-1
CPU for Devices
with M4K® Core
2
Section 2. CPU for Devices with M4K® Core
HIGHLIGHTS
This section of the manual contains the following topics:
2.1 Introduction................................................................................................................2-2
2.2 Architecture Overview ............................................................................................... 2-3
2.3 PIC32 CPU Details .................................................................................................... 2-6
2.4 Special Considerations When Writing to CP0 Registers ......................................... 2-11
2.5 Architecture Release 2 Details ................................................................................ 2-12
2.6 Split CPU bus .......................................................................................................... 2-12
2.7 Internal System Busses........................................................................................... 2-13
2.8 Set/Clear/Invert........................................................................................................2-13
2.9 ALU Status Bits........................................................................................................ 2-14
2.10 Interrupt and Exception Mechanism ........................................................................2-14
2.11 Programming Model ................................................................................................ 2-14
2.12 Coprocessor 0 (CP0) Registers............................................................................... 2-21
2.13 MIPS16e® Execution ............................................................................................... 2-55
2.14 Memory Model......................................................................................................... 2-55
2.15 CPU Instructions, Grouped By Function.................................................................. 2-56
2.16 CPU Initialization ..................................................................................................... 2-59
2.17 Effects of a Reset ....................................................................................................2-60
2.18 Related Application Notes ....................................................................................... 2-61
2.19 Revision History....................................................................................................... 2-62
PIC32 Family Reference Manual
DS61113E-page 2-2 © 2007-2012 Microchip Technology Inc.
2.1 INTRODUCTION
The PIC32 MCU is a complex system-on-chip (SoC) that is based on the M4K
® Microprocessor
core from MIPS® Technologies. The M4K® is a state-of-the-art, 32-bit, low-power, RISC proces-
sor core with the enhanced MIPS32® Release 2 Instruction Set Architecture (ISA).
This chapter provides an overview of the CPU features and system architecture of the PIC32
family of microcontrollers that are based on the M4K
® processor core.
2.1.1 Key Features
Up to 1.5 DMIPS/MHz of performance
Programmable prefetch cache memory to enhance execution from Flash memory (not
available on all devices; refer to the specific device data sheet to determine availability)
16-bit Instruction mode (MIPS16e
®) for compact code
Vectored interrupt controller with up to 96 interrupt sources
Programmable User and Kernel modes of operation
Atomic bit manipulations on peripheral registers (Single cycle)
Multiply-Divide unit with a maximum issue rate of one 32 x 16 multiply per clock
High-speed Microchip ICD port with hardware-based non-intrusive data monitoring and
application data streaming functions
EJTAG debug port allows extensive third party debug, programming and test tools support
Instruction controlled power management modes
Five-stage pipelined instruction execution
Internal code protection to help protect intellectual property
2.1.2 Related MIPS® Documentation
• MIPS32® M4K® Processor Core Software User’s Manual – MD00249-2B-M4K-SUM
• MIPS® Instruction Set – MD00086-2B-MIPS32BIS-AFP
• MIPS16e® – MD00076-2B-MIPS1632-AFP
• MIPS32® Privileged Resource Architecture – MD00090-2B-MIPS32PRA-AFP
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all PIC32 devices.
Please consult the note at the beginning of the “CPU” chapter in the current device
data sheet to check whether this document supports the device you are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com
© 2007-2012 Microchip Technology Inc. DS61113E-page 2-3
Section 2. CPU for Devices with M4K® Core
CPU for Devices
with M4K® Core
2
2.2 ARCHITECTURE OVERVIEW
The PIC32 family of devices are complex systems-on-a-chip that contain many features.
Included in all processors of the PIC32 family is a high-performance RISC CPU, which can be
programmed in 32-bit and 16-bit modes, and even mixed modes. PIC32 devices contain a
high-performance interrupt controller, DMA controller, USB controller, in-circuit debugger,
high-performance switching matrix for high-speed data accesses to the peripherals, and on-chip
data RAM memory that holds data and programs. The unique prefetch cache and prefetch buffer
for the Flash memory, which hides the latency of the Flash, provides zero Wait state equivalent
performance.
Figure 2-1: PIC32 Block Diagram
JTAG/BSCAN Priority Interrupt
Controller LDO VREG
DMAC ICD
PIC32 CPU
IS DS
EJTAG INT
Bus Matrix
Prefetch Cache Data RAM
Peripheral
Flash Memory
Flash Controller
Clock Control/
Generation Reset Generation
PMP/PSP
PORTS
ADC
RTCC
Timers
Input Capture
PWM/Output
Compare
Dual Compare
SSP/SPI
I2C™
UART
128-bit
USB
Bridge
CAN(1)
Motor Control
PWM(1)
DAC(1)
CTMU(1)
Note 1: This peripheral is not available on all devices. Refer to the specific device data sheet for
availability.
ETH(1)


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