Microchip PIC24FJ64GA008 Bedienungsanleitung


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© 2008 Microchip Technology Inc. DS39768D-page 1
PIC24FJXXXGA0XX
1.0 DEVICE OVERVIEW
This document defines the programming specification
for the PIC24FJXXXGA0XX family of 16-bit micro-
controller devices. This programming specification is
required only for those developing programming support
for the PIC24FJXXXGA0XX family. Customers using
only one of these devices should use development
tools that already provide support for device
programming.
This specification includes programming specifications
for the following devices:
2.0 PROGRAMMING OVERVIEW
OF THE PIC24FJXXXGA0XX
FAMILY
There are two methods of programming the
PIC24FJXXXGA0XX family of devices discussed in
this programming specification. They are:
In-Circuit Serial Programming™ (ICSP™)
Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
The ICSP programming method is the most direct
method to program the device; however, it is also the
slower of the two methods. It provides native, low-level
programming capability to erase, program and verify
the chip.
The Enhanced In-Circuit Serial Programming
(Enhanced ICSP) protocol uses a faster method that
takes advantage of the programming executive, as
illustrated in Figure 2-1. The programming executive
provides all the necessary functionality to erase, pro-
gram and verify the chip through a small command set.
The command set allows the programmer to program
the PIC24FJXXXGA0XX devices without having to
deal with the low-level programming protocols of the
chip.
FIGURE 2-1: PROGRAMMING SYSTEM
OVERVIEW FOR
ENHANCED ICSP™
This specification is divided into major sections that
describe the programming methods independently.
Section 4.0 “Device Programming Enhanced
ICSP describes the Run-Time Self-Programming
(RTSP) method. Section 3.0 “Device Programming
ICSP describes the In-Circuit Serial Programming
method.
2.1 Power Requirements
All devices in the PIC24FJXXXGA0XX family are dual
voltage supply designs: one supply for the core and
peripherals and another for the I/O pins. A regulator is
provided on-chip to alleviate the need for two external
voltage supplies.
All of the PIC24FJXXXGA0XX devices power their core
digital logic at a nominal 2.5V. To simplify system
design, all devices in the PIC24FJXXXGA0XX family
incorporate an on-chip regulator that allows the device
to run its core logic from VDD.
• PIC24FJ16GA002 • PIC24FJ96GA006
• PIC24FJ16GA004 • PIC24FJ96GA008
• PIC24FJ32GA002 • PIC24FJ96GA010
• PIC24FJ32GA004 PIC24FJ128GA006
• PIC24FJ48GA002 PIC24FJ128GA008
• PIC24FJ48GA004 PIC24FJ128GA010
• PIC24FJ64GA002
• PIC24FJ64GA004
• PIC24FJ64GA006
• PIC24FJ64GA008
• PIC24FJ64GA010
PIC24FJXXXGA0XX
Programmer Programming
Executive
On-Chip Memory
PIC24FJXXXGA0XX Flash Programming Specification
PIC24FJXXXGA0XX
DS39768D-page 2 © 2008 Microchip Technology Inc.
The regulator provides power to the core from the other
VDD pins. A low-ESR capacitor (such as tantalum) must
be connected to the VDDCORE pin (Figure 2-2 and
Figure 2-3). This helps to maintain the stability of the
regulator. The specifications for core voltage and capac-
itance are listed in Section 7.0 “AC/DC Characteristics
and Timing Requirements”.
FIGURE 2-2: CONNECTIONS FOR THE
ON-CHIP REGULATOR
(64/80/100-PIN DEVICES)
FIGURE 2-3: CONNECTIONS FOR THE
ON-CHIP REGULATOR
(28/44-PIN DEVICES)
VDD
ENVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA0XX
CEFC
3.3V
Regulator Enabled (ENVREG tied to VDD):
(10 μF typ)
Note 1: These are typical operating voltages. Refer
to
Section 7.0 “AC/DC Characteristics and
Timing Requirements”
for the full operating
ranges of VDD and VDDCORE.
VDD
ENVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA0XX
3.3V(1)
2.5V(1)
Regulator Disabled (ENVREG tied to ground):
VDD
ENVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA0XX
2.5V(1)
Regulator Disabled (VDD tied to VDDCORE):
VDD
DISVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA0XX
3.3V(1)
2.5V (1)
Regulator Disabled (DISVREG tied to VDD):
VDD
DISVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA0XX
2.5V(1)
Regulator Disabled (VDD tied to VDDCORE):
VDD
DISVREG
VDDCORE/VCAP
VSS
PIC24FJXXXGA0XX
CEFC
3.3V
(10 μF typ)
Regulator Enabled (DISVREG tied to V SS):
Note 1: These are typical operating voltages. Refer
to
Section 7.0 “AC/DC Characteristics and
Timing Requirements
for the full operating
ranges of VDD and VDDCORE.
© 2008 Microchip Technology Inc. DS39768D-page 3
PIC24FJXXXGA0XX
2.2 Program Memory Write/Erase
Requirements
The Flash program memory on the PIC24FJXXXGA0XX
devices has a specific write/erase requirement that must
be adhered to for proper device operation. The rule is
that any given word in memory must not be written more
than twice before erasing the page in which it is located.
Thus, the easiest way to conform to this rule is to write
all the data in a programming block within one write
cycle. The programming methods specified in this
specification comply with this requirement.
2.3 Pin Diagrams
The pin diagrams for the PIC24FJXXXGA0XX family
are shown in the following figures. The pins that are
required for programming are listed in Table 2-1 and
are shown in bold letters in the figures. Refer to the
appropriate device data sheet for complete pin
descriptions.
TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING)
Note: Writing to a location multiple times without
erasing is not recommended.
Pin Name
During Programming
Pin Name Pin Type Pin Description
MCLR MCLR P Programming Enable
ENVREG ENVREG I Enable for On-Chip Voltage Regulator
DISVREG(1) DISVREG I Disable for On-Chip Voltage Regulator
VDD and AVDD(2) VDD P Power Supply
VSS and AVSS(2) VSS P Ground
VDDCORE VDDCORE P Regulated Power Supply for Core
PGC1 PGC I Primary Programming Pin Pair: Serial Clock
PGD1 PGD I/O Primary Programming Pin Pair: Serial Data
PGC2 PGC I Secondary Programming Pin Pair: Serial Clock
PGD2 PGD I/O Secondary Programming Pin Pair: Serial Data
Legend: I = Input, O = Output, P = Power
Note 1: Applies to 28 and 44-pin devices only.
2: All power supply and ground pins must be connected, including analog supplies (AVDD) and ground
(AVSS).


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Marke: Microchip
Kategorie: Nicht kategorisiert
Modell: PIC24FJ64GA008

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