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 2008-2015 Microchip Technology Inc. DS80000425P-page 1
PIC18F24K20/25K20/44K20/45K20
The PIC18F24K20/25K20/44K20/45K20 devices that
you have received conform functionally to the current
Device Data Sheet (DS41303H), except for the
anomalies described in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in . The silicon issues are summarized inTable 1
Table 2.
The errata described in this document will be addressed
in future revisions of the PIC18F24K20/25K20/44K20/
45K20 silicon.
Data Sheet clarifications and corrections start on page
13, following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB® IDE and Microchip’s
programmers, debuggers, and emulation tools, which
are available at the Microchip corporate web site
(www.microchip.com).
For example, to identify the silicon revision level
using MPLAB IDE in conjunction with a hardware
debugger:
1. Using the appropriate interface, connect the
device to the hardware debugger.
2. Open an MPLAB IDE project.
3. Configure the MPLAB IDE project for the
appropriate device and hardware debugger.
4. Based on the version of MPLAB IDE you are
using, do one of the following:
a) For MPLAB IDE 8, select Programmer >
Reconnect.
b) For MPLAB X IDE, select Window >
Dashboard and click the Refresh Debug
Tool Status icon ( ).
5. Depending on the development tool used, the
part number and Device Revision ID value
appear in the Output window.
The DEVREV values for the various PIC18F24K20/
25K20/44K20/45K20 silicon revisions are shown in
Table 1.
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2 apply to the current silicon revi-
sion (AF).
Note: If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
TABLE 1: SILICON DEVREV VALUES
Part Number Device ID(1) (11-bit)
Revision ID for Silicon Revision
(2) (5-bit)
A4 A7 A9 AB A4 A7 A8 AE AF
PIC18F24K20 105h 0xA 0xC 0xE 0x11 0x16 0x18 0x19 0x1B 0x1C
PIC18F25K20 103h 0xA 0xC 0xE 0x11 0x16 0x18 0x19 0x1B 0x1C
PIC18F44K20 104h 0xA 0xC 0xE 0x11 0x16 0x18 0x19 0x1B 0x1C
PIC18F45K20 102h 0xA 0xC 0xE 0x11 0x16 0x18 0x19 0x1B 0x1C
Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration
memory space. They are shown in hexadecimal in the format “DEVID:DEVREV”.
2: Refer to the “PIC18F2XK20/4XK20 Flash Memory Programming Specification” (DS41297) for detailed
information on Device and Revision IDs for your specific device.
3: Shaded cells in this table indicate older device revisions that are no longer in production.
PIC18F24K20/25K20/44K20/45K20
Silicon Errata and Data Sheet Clarification
PIC18F24K20/25K20/44K20/45K20
DS80000425P-page 2  2008-2015 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature Item
Number Issue Summary
Affected Revisions(1)
A4
A7
A9
AB
A4
A7
A8
AE
AF
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
ECCP CCP1CON 1. Changing CCP1M bits may
cause capture of Timer1 value.
X X X X
ECCP Full-Bridge
mode
2. Direction change issue. X X X X
MSSP SPI SPI Clock 3. Shortened SPI high time. X X X X
MSSP I2CSlew Rate 4. Slow slew rate when
SLRCON<2> is set.
X X X X
ADC Offset 5. Time dependent on offset. X X X X
MSSP I2CReceiving 6. Address may be received as
data.
X X X X
MSSP I2CMaster mode 7. Master mode not functional. X
MSSP SPI SPI Master 8. Improper sampling of last bit. X X X X
MSSP SPI SPI Master 9. SSPBUF improperly reloads on
SS pin transitions.
X X X X
MSSP SPI SPI Master 10. Improper extra pulse on SCK
pin.
X X X X
EUSART Synchronous
Master mode
11. Duty cycle of CK output is
skewed when SPBRG is odd.
X X X X
EUSART Synchronous
Master mode
12. LS bit corruption during
transmission when SPBRG = 3.
X X X X
EUSART Synchronous
Master mode
13. Clock fails to stop at end of
character transmission when
SPBRG = 0.
X X X X
Internal Fixed
Voltage Refer-
ence (FVR)
—14. FVRST bit activates prematurely. X X
High Low Voltage
Detect (HLVD)
—15. IVRST bit activates prematurely. X X
BOR FVR 16. Unexpected BOR occurrence. X X
System Clocks —17. HFINTOSC output accuracy. X X X X
POR/BOR —18. Unexpected code execution at
low VDD.
X X X X
POR —19. Premature POR release. X X X X
POR —20. POR may become stuck. X X X X
Clocks EC mode 21. 48 MHz maximum frequency. X X
Comparators Interrupt-on-
Change
22. Presetting interrupt-on-change
issue.
X X X X
Data EEPROM
Memory
Endurance 23. Endurance is limited to 10K
cycles.
X X X X X X X
Program Flash
Memory
Endurance 24. Endurance is limited to 1K
cycles.
X X X X X X X
Configuration Bits CONFIG3H 25. HFOFST bit erases to ‘0’ instead
of ‘1’.
X X X X
Note 1: Only those issues indicated in the last column apply to the current silicon revision.
2: Shaded cells in this table indicate older device revisions that are no longer in production.
 2008-2015 Microchip Technology Inc. DS80000425P-page 3
PIC18F24K20/25K20/44K20/45K20
EUSART Asynchronous
Receive mode
26. RCIDL bit may stay low
improperly.
X X X X
PORTB Interrupts Interrupt-on-
Change
27. False interrupt when setting
interrupt enable.
X X X X X X X X X
ADC ADC
Conversion
28. ADC conversion may be limited
to half scale.
X X X X X X X
ECCP Full-Bridge
mode
29. Wrong dead-band time. X X X X X X X X X
ECCP Full-Bridge
mode
30. Wrong signal start time. X X X X X X X X X
MSSP SPI SPI Clock 31. Improper SCK output. X X X X X X X X X
MSSP SPI SPI Master 32. Improper sampling of last bit. X X X X X X X X X
MSSP SPI SPI Master 33. Improper handling of write
collision.
X X X X X X X X X
MSSP I2CI2C Master 34. Improper handling of Stop event. X X X X X X X X X
EUSART OERR Flag 35. Clearing SPEN bit does not clear
OERR flag.
X X X X X X X X X
EUSART BAUDCTL 36. RCIDL bit may stay low
improperly.
X X X X X X X X X
PORTB Interrupts Interrupt-on-
Change
37. False interrupt when waking
from Sleep.
X X X X X X X X X
BOR Reset 38. Reset on configuring the analog
comparators to the FVR.
X X X X X X X X X
Wake-up from
Low-Power Sleep
mode
Wake-up
Sources
39. Device may not wake-up under
specific conditions.
X X X X X X X X X
Low-Voltage
Detect
LVD in Sleep 40. LVD erroneously triggers upon
wake-up from Sleep if band gap
is disabled in Sleep mode.
X X X X X X X X X
Timer1/3 Interrupt 41. When the timer is operated in
Asynchronous External Input
mode, unexpected interrupt flag
generation may occur.
X X X X X X X X X
TABLE 2: SILICON ISSUE SUMMARY (CONTINUED)
Module Feature Item
Number Issue Summary
Affected Revisions(1)
A4
A7
A9
AB
A4
A7
A8
AE
AF
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
Note 1: Only those issues indicated in the last column apply to the current silicon revision.
2: Shaded cells in this table indicate older device revisions that are no longer in production.

Produktspezifikationen

Marke: Microchip
Kategorie: Nicht kategorisiert
Modell: PIC18F45K20

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