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- 6 Voltage-Mode, Current-Mode (and Hysteretic Control) TN 20
by Sanjaya Maniktala
Copyright © 2012 Page 1 Microsemi
Rev 0.5 - -12 Analog Mixed Signal Group / 07 30
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756- 0308
Introduction
Switching regulators have been with us for many years. They were considered tricky to design –
and still are. In 1976 Silicon General (later LinFinity, then Microsemi), introduced the irst
monolithic (IC-based) switching controller, the SG1524 “Pulse Width Integrated Circuit”. A little
later, this chip was improved and became the “SG3524” historic industry workhorse. And very soon
thereafter, it was available from multiple chip vendors. Keep in mind that switching stages based on
discrete designs were already gaining ground, particularly in military applications. In fact, some
resourceful engineers had even made “switch mode power supplies” by adding related circuitry -
around one of the highest-selling chips in history: the “555 timer” (sometimes called the “IC Time
Machine”), introduced in 1971 by Signetics (later Philips, then NXP). The SG1524 was however the
irst all IC in which the required control functionality was present on a single chip/die. With the
rapidly escalating concurrent interest in switching power supplies at the time, it is no surprise that
as early as 1977 the very irst book on the subject, written by the late Abraham Pressman, appeared
on the scene. Together, these events spurred interest in an area well beyond most people’s
expectations, and ushered in the world of switching power conversion as we know it today.
The SG1524/3524 drove a pair of (bipolar) switching transistors with a “duty cycle” (ratio of switch
ON-time to the total time period) which was proportional to the “control voltage”. By using switching
transistors to switch the input voltage source ON and OFF into an LC low pass ilter, a relatively
eficient voltage regulator was produced. At the heart of this regulator was the “PWM (pulse width
modulator) comparator”. The output pulse-train to drive the transistors with was a result of
applying a (relatively) smooth control voltage on one of this comparator’s input terminals, along
with a “sawtooth” or “PWM ramp” a generated from the clock Figure 1, on its other input. See . This
technique is known as "voltage-mode programming”, or “voltage mode control” (“VMC”) –- since the
duty cycle is proportional to the control voltage. The control voltage is in effect the difference
between the actual output voltage and the “reference” value (the value we want to fix the output at,
i.e. the “setpoint”). We will discuss this igure in more detail shortly.
Another well-known technique today, which has also been around since the 80s, senses the peak
current in the power switch or inductor, and turns the switch OFF at a programmed level of
current. This technique is called current-mode control (“CMC”). Keep in mind it was not brand-“
new at the time. In fact it had been discovered years ago, but few had realized its signiicance till ”
Unitrode Corp. (now Texas Instruments) came along. It received a huge boost in popularity in the
form of the world’s first current-mode control (CMC) chip, the Flyback controller UC1842 from
Unitrode In CMC, there is in effect a (fast-. acting) “inner” current loop along with the “outer”
(slower) “voltage loop” which carries out the output regulation. See the note on ramp generation
within , indicating how this particular aspect is different between VMC and CMC. Prima Figure 1
- 6 Voltage-Mode, Current-Mode (and Hysteretic Control) TN 20
by Sanjaya Maniktala
Copyright © 2012 Page 2 Microsemi
Rev 0.5 - -12 Analog Mixed Signal Group / 07 30
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756- 0308
facie, CMC seems to be better. “Pulse- -by pulse” became synonymous with CMC. It was once even
thought to be the silver bullet, or magic wand, to ix that everything voltage-mode control was not.
The UC1842 was later improved to UC3842, and shortly thereafter, following the success story of
the 3524, the UC3842 was soon available from innumerable chip vendors. But a few years into SG
this success story, expectations got somewhat blunted.
The disadvantages of CMC surfaced slowly. That growing realization was succinctly summed up in a
well-known Design Note - –DN 62 – from Unitrode, which said: “there is no single topology which is
optimum for all applications. Moreover, voltage-mode control If updated with modern circuit and –
process developments – has much to offer designers of today's high-performance supplies and is a
viable contender for the power supply designer's attention. it is reasonable to expect ” It also says: “
some confusion to be generated with the introduction of the UCC3570 a new voltage-mode controller –
introduced almost 10 years after we told the world that current-mode was such a superior approach.”
To put things in perspective, the above-mentioned design note was written by “the father of the
PWM controller IC industry,” Bob Mammano, who developed the first voltage-mode control IC, the
SG1524. Later, as Staff Technologist in the Power IC division of Unitrode (a division that p2-he had
jointly created with two others from Silicon General), Mammano led the development of the first
current-mode control IC, the UC1842.
NP:NS
+
-
VCOMP
EA-output
{
{
VO
{
VIN
POWER STAGE
CONTROL SECTION
Transformer
(optional)
Feedback trace
Driver
not shown
+
-
V
REF
VFB
EA-input
ERROR
AMP
{
Divider
(Sensor)
{
optocoupler
(optional)
CONTROL
OUTPUT
“LINE”
REFERENCE
Rf2
Rf1
Control voltage
OUTPUT
∑
INPUT
(LINE)
REFERENCE
-
+
FB pin
CONTROL
EA OUT/
Control Voltage/
COMP pin
DividerError Amp
PWM
Comparator Switch LC Post Filter
Equivalent
PLANT
FEEDBACK
PLANT
FEEDBACK
Rf2
Rf1
VIN
In Current Mode Control, the “RAMP” is
generated from the Inductor Current
RAMP RAMP
G(s)
H(s)
PLANT
FEEDBACK (COMPENSATOR)
Figure 1: Voltage and Current Mode Regulators with their shared Functional Blocks
- 6 Voltage-Mode, Current-Mode (and Hysteretic Control) TN 20
by Sanjaya Maniktala
Copyright © 2012 Page 3 Microsemi
Rev 0.5 - -12 Analog Mixed Signal Group / 07 30
1 Enterprise, Aliso Viejo, CA 92656, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756- 0308
Building Blocks of Switching Regulators and Stability
In , we see the building blocks of a typical switching regulator. TFigure 1 here is a “power stage”,
consisting of switch/diode, inductor/transformer, and input/output caps. The input “V
IN” comes
into this block and gets converted into the output, V
O. Around this block is the “control section”
block, consisting essentially of a voltage divider, an error ampliier, and a PWM comparator. In
classic voltage mode control, the voltage ramp to the PWM comparator is ixed, and is artiicially
generated from the clock. In current mode control, this ramp is the sensed inductor/switch current
mapped into a proportional voltage ramp that is applied to the PWM comparator. Keep in mind that
in both VMC and CMC there is a clock, and its basic function is to determine the moment the switch
turns ON in every cycle. The moment at which the switch turns OFF within each cycle is determined
by the “feedback loop”. By using a clock, we ensure a constant repetition rate, or constant switching
frequency, something that is considered desirable for switching regulators, particularly for
complying with EMI limits.
Note: and “Hysteretic controllers”, discussed later, typically dispense with the error amplifier and the clock (
though they retain something quite similar to the PWM comparator, they implement it in a very different
manner). Therefore, trying to keep a constant switching frequency in that case becomes a major design
challenge.
On the right side of , we show how the switching regulator can be mentally partitioned and Figure 1
visualized when discussing loop stability. Notice the terminology in use. We see that the PWM
comparator is considered part of the “Plant”, along with the power stage, and the rest falls into the
“Feedback” section also called the “Compensator”. Their respective transfer functions are denoted
as G(s) and H(s) respectively.
In the mathematical treatment of loop stability, we define a “transfer function”, which is basically
the output of a given block divided by its input. The output and input do not have to be voltages, or
currents, or even similar parameters. For example, the output of the PWM comparator is the “duty
cycle” whereas its input is the “control voltage” (output of the error amplifier). The magnitude of
this transfer function is called its “gain” and its argument is its “phase”. Sometimes, the transfer
function itself is just called the (complex) “gain”.
Objectives and Challenges of Loop Design
The entire purpose of loop stability consists of two tasks. is to discover what G(s) (the plant First
transfer function) , i.e. its Gain-Phase plot with all its inherent is “poles” and “zeros”. The second to is
design the compensator (feedback section) accordingly, such that its poles and zeros are “correctly
located” with respect to those from the plant. What “correct location”does mean? The criterion for
that is based on what we want the “open loop gain” to look like. In -Figure 1 overall gain, the going

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Modell: LX7167

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