Microchip FDC37C669 Bedienungsanleitung

Microchip Nicht kategorisiert FDC37C669

Lesen Sie kostenlos die 📖 deutsche Bedienungsanleitung für Microchip FDC37C669 (3 Seiten) in der Kategorie Nicht kategorisiert. Dieser Bedienungsanleitung war für 5 Personen hilfreich und wurde von 2 Benutzern mit durchschnittlich 4.5 Sternen bewertet

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A A
B B
C C
D D
FDD 1 & 2
Place Bypass Caps close to IC's.
Power and GND to SMC's device must be as heavy as possible, preferably planes
necessarily given. The information has been carefully checked and
is believed to be entirely reliable. However, no responsibility
not convey to the purchaser of the semiconductor devices described
any licence under the patent rights of SMC or others. SMC reserves
Circuit diagrams utilizing SMC products are included as a means
of illustrating typical semiconductor applications; consequently
complete information sufficient for construction purposes is not
is assumed for innaccuracies. Furthermore, such information does
Designed using Orcad 386+ v1.2
16-Bit Addressing
on the POWER layer. Connect this isolated
supply to the board supply through the TJ
Note 1. Isolate the FDC37C669 VCC from the board VCC
jumper.
SYSOPT JUMPER
and supply the best product possible.
the right to make changes at any time in order to improve design
Note 2
The board presently has
a connection to Vcc at
this pin.
FDC37C669 SUPER I/O EVALUATION BOARD
ISA
PORTS
Note 2. This GND connection must
be made on the Rev A EVB.
Wednesday, June 12, 1996
6060-SS- A
FDC37C669 SUPER I/O EVALUATION BOARD
STANDARD MICROSYSTEMS CORPORATION
300 Kennedy Drive
Hauppauge, New York 11788
C
1 3
Title
Size Document Number Rev
Date: Sheet of
ISA, BOOT ROM & WW
ISA.SCH
D[15:0]
ISA[0..9]
IDE[4]
A[0..15]
RH[0..13]
IDE, PP, COM, GAME
PORTS.SCH
IRTX2
IRRX2
IRTX
IRRX
RVOP[1..10]
DRIN[1..6]
nGAMECS
D[15:0]
PD[0..7]
ISA[0..4]
PP[0..8]
IDE[0..4]
A[0..2]
DRV2ISA9
ADRXISA8
DRV2ISA9
ADRXISA8
RH13 IRQ_15
DRIN3
IRTX
RVOP3
IRRX
IOCHRDYISA7
DACK_3#RH4
IRQ_7RH10
DRQ_3RH5
A10
nGAMECS
DRIN6
RVOP10
nSTROBE PP0 IRRX
nAUTOFD PP1
nERROR PP2
nINIT PP3
nSLCTIN PP4 IRTX
PD0
PD1
PD2 IRRX2
PD3
PD4
IDEEN#IDE3 PD5 IRTX2
PD6
PD7
IRQ_14RH11 ACK PP5
IRQ_10RH12 BUSY PP6 nGAMECS
DRQ_1RH1 PE PP7
DACK_1#RH0 SLCT PP8
HDCS0#IDE0
RSTDRV ISA2
D7
D6
IRRX2 D5
A0
D4
A1
DRQ_2 RH3
HDCS1#IDE1 IDE2 IDE_IRQ
A2
D3
IRQ_14RH11
IRTX2
See Note 1.
TCISA5
ISA1 IOR#
ISA0 IOW#
ISA6 AEN
A15
A14
DACK_2#RH2
A13 IRQ_3RH6
A12 IRQ_4RH7
A11 IRQ_5RH8
IRQ_6RH9
DRIN[1..6]
RVOP[1..10]
RH[0..13]
ISA[0..9]ISA[0..9]
A[0..15]A[0..15]
PP[0..8]PP[0..8]
D[15:0]D[15:0]
PD[0..7]PD[0..7]
IDE[0..4]IDE[0..4]
A3
A4
A5
A6
DRIN1
RVOP1
DRIN2
RVOP2 A7
A8
A9
RVOP4
RVOP5
RVOP6
RVOP7
DRIN4 D0
RVOP8 D1
DRIN5 D2
RVOP9
GND
VCC
VCC
GND
GND
GND
GND
GND
GND
VCC
GND
GND
VCC
GND
J4
HEADER17X2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
RWC
HDL
DS3
IDX
DS0
DS1
DS2
MOT ON
DIRC
STEP
WD
WG
TR00
WP
RD DATA
SIDE 1
DSK CHNG
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C30
0.1uF
C31
0.1uF
C32
0.1uF
C33
0.1uF
C36
0.1uF
C37
0.1uF
C38
0.1uF
C39
0.1uF
C40
0.1uF
C41
0.1uF
C42
0.1uF
C43
0.1uF
C44
0.1uF
C45
0.1uF
C46
0.1uF
U6
FDC37C669
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
99
98
97
96
95
94
93
92
91
90
89
88
86
85
84
87
100
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
83
DRVDEN0
MTR0#
DS1#
DS0#
MTR1#
VSS
DIR#
STEP#
WDATA#
WGATE#
HDSEL#
INDEX#
TRK0#
WRTPRT#
VCC
RDATA#
DSKCHG#
DRVDEN1
IRQ_A
CLK14
DRQ_A
DACK_A#
IRQIN
IDEEN#/IRQ_H
HDCS0#/IRRX2
HDCS1#/IRTX2
CS#
A0
A1
A2
DRQ_C
IRQ_G
A10
DACK_C#
VSS
DRV2/ADRX/IRQ_B
DTR2#
CTS2#
RTS2#
DSR2#
TXD2/IRTX
RXD2/IRRX
RI2#
DCD1#
RI1#
DCD2#
IOCHRDY
CTS1#
RTS1#
A3
A4
A5
A6
TC
DACK_B#
IRQ_C
IRQ_D
IRQ_E
IRQ_F
A7
A8
A9
IOR#
IOW#
AEN
VSS
D0
D1
D2
D3
DRQ_B
D4
D5
D6
D7
RESET
PWRGD/GAMECS#
SLCT
PE
BUSY
ACK#
PD7
PD6
PD5
PD4
VSS
PD3
PD2
PD1
PD0
VCC
SLCTIN#
INIT#
ERROR#
AUTOFD#
STROBE#
RXD1
TXD1
DSR1#
DTR1#
U7
XTAL OSC
14.318MHz
1
5
NC
OUTPUT
U8A
74LS27
1
2
13
12
U8B
74LS27
3
4
5
6
U9A
74LS00
1
2
3
JP12
1
2
3
JP13 1
2
3
JP14
1
2
3
JP15
1
2
3
JP17
1
2
3
TJ2
JP19 R37
1K
JP21
1
2
3
JP22
1
2
3
RN2
5x1K
2
3
4
5
6
1
R1
R2
R3
R4
R5
COM
R45
47K
R46
820
JP23
1
2
3
JP10
HEADER 3X2
1 2
3 4
5 6
TP3
TP
TP2
TP
TJ1
JP18
1
2
3
C47
0.1uF
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
Use for IRQ pull-ups
if required.
35V
35V
E0
E1
E2
NC
NC
OPTION BOOT ROM
pull-downs
DRQ
WIRE-WRAP AREA
VCC AND GND ARE LOCATED AS SHOWN ON BOARD
ISA
Wednesday, June 12, 1996
6060-SS- A
FDC37C669 EVB ISA.SCH
STANDARD MICROSYSTEMS CORPORATION
C
2 3
Title
Size Document Number Rev
Date: Sheet of
D0 A0
D1 A1
D2 A2
D3 A3
D4 A4
RSTDRVISA2 D7
D6 D5 A5
IRQ9 D5
D4
DRQ2 D3
D2 D6 A6
D1
D0
IOCHRDY ISA7 IOCHRDYISA7
AEN ISA6
IDE_IOCHRDY IDE4
D7 A7
A19
IOW#ISA0 A18
IOR#ISA1 A17
DACK3# A16 D8 A8
DRQ3 A15
DACK1# A14
DRQ1 A13
A12 D9 A9
A11
IRQ7 A10
IRQ6 A9
IRQ5 A8 ADRXISA8 D10 A10
IRQ4 A7
IRQ3 A6
DACK2# A5
TCISA5 A4 DRV2ISA9 D11 A11
ALEISA3 A3
A2
A1
IRQ_9RH14 IRQ9 A0 IOR#ISA1 D12 A12
DRQ_2RH3 DRQ2
DACK_3#RH4 DACK3#
DRQ_3RH5 DRQ3
DACK_1#RH0 DACK1# IOW#ISA0 D13 A13
DRQ_1RH1 DRQ1
IRQ_7RH10 IRQ7
IRQ_6RH9 IRQ6
IRQ_5RH8 IRQ5 D14 A14
IRQ_4RH7 IRQ4
IRQ_3RH6 IRQ3
DACK_2#RH2 DACK2# IOCS16#ISA4
IRQ_10RH12 IRQ10 D15 A15
IRQ_11RH15 IRQ11
IRQ_12RH16 IRQ12
IRQ_15RH13 IRQ15
IRQ_14RH11 IRQ14
D8
D9
D10
D11
D12
D13
D14
D15
A13 A0 D0
IRQ_9 RH14 A14 A1 D1
A15 A2 D2
A16 A3 D3
A17 A4 D4
IRQ_11 RH15 A18
JEDECP27
JEDECP27
JEDECP27
A5 D5
A19
JEDECP1
JEDECP1
JEDECP1
A6 D6
DC0
ROMEN*
ROMEN*
ROMEN*
A7 D7
DC1 A8
IRQ_12 RH16 DA0 A9
DA1 A10
DA2 A11
A12
A13
D[15:0]
ISA[0..9]ISA[0..9]
RH[0..16]RH[0..16]
A[0..19]
VCC
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
+12V
-12V
VCC
VCC
VCC
R31
220
TP1
TEST POST
TP
R34
10K
R35
10K
JP7
1
2
J5
CON1
1
JP8
1
2
J6
CON1
1
TP4
TEST POST
TP
J7
CON1
1
TP5
TEST POST
TP
J8
CON1
1
JP16
HEADER 18X2
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
R38
10K
J9
CON1
1
J10
CON1
1
R39
10K
J11
CON1
1
R40
10K
J12
CON1
1
JP5
HEADER 5X2
JEDEC SEL/ADR
L12110
1 2
3 4
5 6
7 8
9 10
J13
CON1
1
RN3
SIP5-10K
2
3
4
5
6
1
R1
R2
R3
R4
R5
COM
U4
20L8
BT1031
L1027
1
2
3
4
5
6
7
8
9
10
11
13
14
23
22
21
20
19
18
17
16
15
24
12
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
I12
I13
I14
O1
O2
O3
O4
O5
O6
O7
O8
VCC
GND
J14
CON1
1
J15
CON1
1
U5
28 pin socket
JEDEC BYTE-WIDE SITE
L1130
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
1
20
22
11
12
13
15
16
17
18
19
28
14
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
CE
OE
O0
O1
O2
O3
O4
O5
O6
O7
VCC
GND
J16
CON1
1
J17
CON1
1
J18
CON1
1
J19
CON1
1
J20
CON1
1
J21
CON1
1
J22
CON1
1
J23
CON1
1
J24
CON1
1
J25
CON1
1
J26
CON1
1
J27
CON1
1
J28
CON1
1
J29
CON1
1
J30
CON1
1
J31
CON1
1
J38
CON1
1
J39
CON1
1
J40
CON1
1
J41
CON1
1
J42
CON1
1
J43
CON1
1
J44
CON1
1
J45
CON1
1
J46
CON1
1
Z1
ISA A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
IO CHK
D7
D6
D5
D4
D3
D2
D1
D0
READY
AEN
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Z2
ISA B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
GND
RESET
VCC
IRQ9
-5V
DRQ2
-12V
OWS
+12
GND
SMEMW
SMEMR
WR
RD
DACK3
DRQ3
DACK1
DRQ1
RFRSH
CLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
DACK2
T/C
BALE
VCC
OSC
GND
P1
HEADER_AT_S
21
43
65
87
109
1211
1413
1615
1817
2019
2221
2423
2625
2827
3029
3231
3433
3635
C1D1
C2D2
C3D3
C4D4
C5D5
C6D6
C7D7
C8D8
C9D9
C10D10
C11D11
C12D12
C13D13
C14D14
C15D15
C16D16
C17D17
C18D18
JP1
1
2
C20
22uF
C21
0.1uF
C22
22uF
C23
0.1uF
C24
22uF
C25
0.1uF
C26
0.1uF
C27
0.1uF
C28
22uF
C29
22uF
D1
LED
D[15:0]
RH[0..13]
ISA[0..9]
IDE[0..4]
A[0..15]
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
COMM 1
COMM 2
with Bipolar drivers and receivers
SINGLE GAME PORT
J2 pinout set for std. 16-pin header to 15-pin D
COM1, COM2 AND IR
Alternate IR
Primary IR
Short for uSoft
compatibility test
IDE DRIVE
DRIVE ACTIVITY LED
HIGH BYTE
BUFFER
BUFFER
LOW BYTE
16 BIT IDE
PORTS
Wednesday, June 12, 1996
6060-SS- A
FDC37C669 EVB PORTS.SCH
STANDARD MICROSYSTEMS CORPORATION
C
3 3
Title
Size Document Number Rev
Date: Sheet of
IRRX
IRTX
IRRX2
IRTX2
HDCS0#IDE0 HDCS1# IDE1
A0 A2
A1
IDE_IRQIDE2 IOCS16# ISA4
IDE_IOCHRDYIDE4 ALE ISA3
IOR#ISA1
IOW#ISA0
D0 D15
RVIN7 D1 D14
DROP4 D2 D13
RVIN8 IRRX D3 D12
DROP6 D4 D11
DROP5 IRTX D5 D10
RVIN10 D6 D9
RVIN6 RVIN9 D7 D8
RVIN9 IOW# ISA0 RVIN6 RSTDRV#
IOR# ISA1 IDEEN#IDEEN# IDE3
D6 IOR# ISA1
D5
D4
D3
D2 RVIN5
D1 DROP2
D0 DROP3 IRRX2
RSTDRV ISA2 RVIN4
IRTX2
RVOP10 RVIN3
DROP1
RSTDRV# RVOP9 RVIN2
RVIN1
nGAMECS nSTROBEPP0
STB#(DS0#)STB#(DS0#)
nAUTOFDPP1
ERR#(HDSEL#)
nERRORPP2
ERR#(HDSEL#)
ALF#(DRVDEN0)ALF#(DRVDEN0)nINITPP3
nSLCTINPP4
PD0
PD0(INDEX#)
PD1(TRK0#)PD1(TRK0#)
PD1 INIT#(DIR#)INIT#(DIR#)
PD2 PD2(WP#)PD2(WP#)
PD3 SLCTIN(WGATE#)SLCTIN(WGATE#)
PD3(RDATA)PD3(RDATA)
PD4
PD5 PD4(DSKCHG#)PD4(DSKCHG#)
PD6
PD7 PD5(MID0)PD5(MID0)
ACK#(DS1#)
ACKPP5
ACK#(DS1#)
BSY(MTR1#)
BUSYPP6
BSY(MTR1#)
PD6(MTR0#)PD6(MTR0#)
PE(WDATA#)
PEPP7
PE(WDATA#)
SCLT(STEP#)
SLCTPP8
SCLT(STEP#)
PD7(MID1)PD7(MID1)
IDE[0..7]IDE[0..7]
D[15:0]D[15:0]
ISA[0..4]ISA[0..4]
RVOP[1..10]
DRIN[1..6]
PD[0..7]
PP[0..8]
DROP5 RVOP1
RVIN7
RVIN8 RVOP2
RVIN10 RVOP3
DROP4 RVOP4
DROP6 DRIN1
RVIN1 DRIN2
RVIN4 DRIN3
DROP2 RVOP5
RVIN3
RVIN2 DRIN4
RVIN5 DRIN5
DROP3 DRIN6
DROP1 RVOP6
RVOP7
RVOP8
VCC
VCC
VCC
VCCVCC
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
GND
-12V
GND
GND
VCC
GND
VCC
VCC
+12V
VCC
VCC
U1
74LS245
2
3
4
5
6
7
8
9
19
1
18
17
16
15
14
13
12
11
A1
A2
A3
A4
A5
A6
A7
A8
G
DIR
B1
B2
B3
B4
B5
B6
B7
B8
U2
74LS245
2
3
4
5
6
7
8
9
19
1
18
17
16
15
14
13
12
11
A1
A2
A3
A4
A5
A6
A7
A8
G
DIR
B1
B2
B3
B4
B5
B6
B7
B8
J1
HEADER 20X2
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
P2
DCON25F
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
R9
4.7K
R10
220
C1
180
JP2
HEADER4
1
2
3
4
C2
180
RN1
4.7KX5
2
3
4
5
6
1R1
R2
R3
R4
R5
COM
C3
180
J2
HEADER8X2
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
C4
180
R29
2.2K
C5
180
C18
.01
C19
.01
C6
180
C7
180
R30
2.2K
C8
180
JP41
2
C9
180
J3
HEADER5X2
12
34
56
78
910
C10
180
U3
SMC34C759
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9
48
SD3
SD4
SD5
SD6
IORIN
IOWIN
GPO1
GPO0
+12V
DROP1
DROP3
RVIN5
RVIN2
RVIN3
DROP2
RVIN4
RVIN1
DROP6
DROP4
RVIN10
RVIN8
RVIN7
DROP5
RVIN6
RVIN9
-12V
GBO1
GBO0
CS1OP
CS0OP
ID6
ID5
ID4
ID3
ID2
ID1
ID0
PDCIN
RVOP1
GND
RVOP2
RVOP3
RVOP4
DRIN1
DRIN2
DRIN3
RVOP5
GMCS
DRIN4
DRIN5
DRIN6
RVOP6
RVOP7
RVOP8
RVOP9
+5V
RVOP10
CS0IN
CS1IN
MR
SD0
SD1
SD2
RSTIDE
C34
0.1uF
C11
180
C12
180
C35
0.1uF
C13
180
R32
4.7K
C14
180
R33
10K
C15
180
JP6
1
2
3
C16
180
C17
180
JP9
4 HEADER
1
2
3
4
R15
1K
R36
100K
R16
1K
R17
1K
JP20
4 HEADER
1
2
3
4
P3
DCON9M
5
9
4
8
3
7
2
6
1
R18
1K
R19
1K
R20
1K
R21
1K
R22
1K
R23
1K
R24
1K
R25
1K
R26
1K
R27
1K
R41
1K
R42
1K
R43
1K
R44
1K
JP3
SH2
1
2
R28
4.7K
R1 33
R2 33
R3 33
R4 33
R5 33
R6 33
R7 33
R8 33
R11 33
R13 33
R12 33
R14 33
nGAMECS
IRRX
IRTX
IRRX2
IRTX2
D[15:0]
DRIN[1..6]
RVOP[1..10]
IDE[0..4]
ISA[0..4]
PD[0..7]
PP[0..8]
A[0..2]

Produktspezifikationen

Marke: Microchip
Kategorie: Nicht kategorisiert
Modell: FDC37C669

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