Microchip dsPIC33EP32MC202 Bedienungsanleitung

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© 2010-2011 Microchip Technology Inc. DS70645C-page 14-1
High-Speed PWM
14
Section 14. High-Speed PWM
HIGHLIGHTS
This section of the manual contains the following major topics:
14.1 Introduction .................................................................................................................. 14-2
14.2 Features....................................................................................................................... 14-2
14.3 Control Registers ......................................................................................................... 14-3
14.4 Architecture Overview................................................................................................ 14-24
14.5 Module Description .................................................................................................... 14-27
14.6 PWM Operating Modes.............................................................................................. 14-33
14.7 PWM Generator......................................................................................................... 14-71
14.8 PWM Trigger.............................................................................................................. 14-87
14.9 PWM Interrupts.......................................................................................................... 14-98
14.10 PWM Fault Pins ......................................................................................................... 14-99
14.11 Special Features ...................................................................................................... 14-105
14.12 PWM Output Pin Control...........................................................................................14-111
14.13 Immediate Update of PWM Duty Cycle ................................................................... 14-113
14.14 Power-Saving Modes............................................................................................... 14-114
14.15 External Control of Individual Time Base(s)............................................................. 14-114
14.16 Application Information ............................................................................................ 14-115
14.17 Register Map............................................................................................................ 14-126
14.18 Related Application Notes........................................................................................ 14-127
14.19 Revision History ....................................................................................................... 14-128
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-2 © 2010-2011 Microchip Technology Inc.
14.1 INTRODUCTION
This section describes the High-Speed Pulse-Width Modulator (PWM) module and its
associated operational modes. The High-Speed PWM module in the dsPIC33E/PIC24E
device family supports a wide variety of PWM modes and is ideal for power
conversion/motor control applications. Some of the common applications include:
• AC-to-DC converters
• DC-to-DC converters
• AC and DC motors: BLDC, PMSM, ACIM, SRM, etc.
• Inverters
• Battery chargers
• Digital lighting
• Uninterrupted Power Supply (UPS)
• Power Factor Correction (PFC) (e.g., Interleaved PFC and Bridgeless PFC)
14.2 FEATURES
The High-Speed PWM module consists of the following major features:
• Up to seven PWM generators, each with an individual time base
• Two PWM outputs per PWM generator
• Individual period and duty cycle for each PWM output
• Duty cycle, dead time, phase shift and frequency resolution equal to the system clock
source (TOSC)
• Independent fault and current-limit inputs for up to 14 PWM outputs
• Redundant Output mode
• Independent Output mode (this feature is not available on all devices)
• Push-Pull Output mode
• Complementary Output mode
• Center-Aligned PWM mode
• Output override control
• Special Event Trigger
• PWM capture feature
• Prescaler for input clock
• ADC triggering with PWM
• Independent PWM frequency, duty cycle and phase shift changes
• Leading-Edge Blanking (LEB) functionality
• Dead time compensation
• Output clock chopping
Note: This family reference manual section is meant to serve as a complement to device
data sheets. Depending on the device variant, this manual section may not apply to
all dsPIC33E/PIC24E devices.
Please consult the note at the beginning of the “High-Speed PWM” chapter in the
current device data sheet to check whether this document supports the device you
are using.
Device data sheets and family reference manual sections are available for
download from the Microchip Worldwide Web site at: http://www.microchip.com
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-3
Section 14. High-Speed PWM
High-Speed PWM
14
14.3 CONTROL REGISTERS
The following registers control the operation of the High-Speed PWM module:
•PTCON: PWM Time Base Control Register
- Enables or disables the High-Speed PWM module
- Sets the Special Event Trigger for the ADC
- Enables or disables immediate period updates
- Selects the synchronizing source for the master time base
- Specifies synchronization settings
•PTCON2: PWM Clock Divider Select Register 2
Provides the clock prescaler to the PWM master time base
•PTPER: Primary Master Time Base Period Register
Provides the PWM time period value
•STCON: PWM Secondary Master Time Base Control Registe (1)
- Enables or disables immediate period updates based on the secondary master time base
- Selects the synchronization source for the secondary master time base
- Specifies the synchronization setting for secondary master time base control
• STCON2: PWM Secondary Clock Divider Select Register 2(1)
Provides the clock prescaler to the PWM secondary master time base
•STPER: Secondary Master Time Base Period Register(1)
Provides the secondary master time base period value
•MDC: PWM Master Duty Cycle Register
Provides the PWM master duty cycle value
•SEVTCMP: PWM Special Event Compare Register
Provides the compare value that is used to trigger the ADC module
•SSEVTCMP: PWM Secondary Special Event Compare Register(1)
Provides the compare value that is used to trigger the ADC module based on the
secondary master time base
•CHOP: PWM Chop Clock Generator Register
- Provides the chop clock frequency
- Enables or disables the chop clock generator
•PWMKEY: PWM Unlock Register(1)
Writes the unlock sequence to allow writes to the IOCONx and FCLCONx registers
•PWMCONx: PWM Control Register
- Enables or disables fault interrupt, current-limit interrupt and primary trigger interrupt
- Provides the interrupt status for fault interrupt, current-limit interrupt and primary trigger
interrupt
- Selects the type of time base (master time base or independent time base)
- Selects the type of duty cycle (master duty cycle or independent duty cycle)
- Controls Dead Time mode
- Enables or disables Center-Aligned mode
- Controls the external PWM Reset operation
- Enables or disables immediate updates of the duty cycle, phase offset, independent time
base period
•IOCONx: PWM I/O Control Register
- Enables or disables PWM pin control feature (PWM control or GPIO)
- Controls fault/current limit override values
- Enables PWMxH and PWMxL pin swapping
- Controls the PWMxH and PWMxL output polarity
- Controls the PWMxH and PWMxL output if any of the following modes is selected:
• Complementary mode
• Push-Pull mode
• True Independent mode
Note: Not all registers are available on all devices. Refer to the “High-Speed PWM”
chapter in the specific device data sheet for availability.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-4 © 2010-2011 Microchip Technology Inc.
•FCLCONx: PWM Fault Current-Limit Control Register
- Selects the current-limit control signal source
- Selects the current-limit polarity
- Enables or disables Current-Limit mode
- Selects the fault control signal source
- Configures the fault polarity
- Enables or disables Fault mode
•PDCx: PWM Generator Duty Cycle Register(1)
- Provides the duty cycle value for the PWMxH and PWMxL outputs, if master time base is
selected
- Provides the duty cycle value for the PWMxH output, if independent time base is selected
•PHASEx: PWM Primary Phase Shift Register
- Provides the phase shift value for the PWMxH and PWMxL output, if master time base is
selected
- Provides the independent time base period for the PWMxH output, if independent time
base is selected
•SDCx: PWM Secondary Duty Cycle Register(1,2)
Provides the duty cycle value for the PWMxL output, if independent time base is selected
•SPHASEx: PWM Secondary Phase Shift Register(1,2,3)
- Provides the phase shift for the PWMxL output, if the master time base is selected
- Provides the independent time base period value for the PWMxL output, if the independent
time base is selected
•DTRx: PWM Dead Time Register
- Provides the dead time value for the PWMxH output, if positive dead time is selected
- Provides the dead time value for the PWMxL output, if negative dead time is selected
•ALTDTRx: PWM Alternate Dead Time Register
- Provides the dead time value for the PWMxL output, if positive dead time is selected
- Provides the dead time value for the PWMxH output, if negative dead time is selected
•TRIGx: PWM Primary Trigger Compare Value Register
Provides the compare value to generate the primary PWM trigger
•TRGCONx: PWM Trigger Control Register
- Enables the PWMx trigger postscaler start event
- Specifies the number of PWM cycles to skip before generating the first trigger
•LEBCONx: Leading-Edge Blanking Control Register
- Selects the rising or falling edge of the PWM output for LEB
- Enables or disables LEB for fault and current-limit inputs
•LEBDLYx: Leading-Edge Blanking Delay Register
Provides leading-edge blanking delay for the fault and current-limit inputs
•PWMCAPx: Primary PWM Time Base Capture Register
Provides the captured independent time base value when a leading edge is detected on
the current-limit input, and when LEB processing on the current-limit input signal is
completed
•AUXCONx: PWM Auxiliary Control Register
- Selects PWM state blank and chop clock sources
- Selects PWMxH and PWMxL output chopping functionality
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-5
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-1: PTCON: PWM Time Base Control Register
R/W-0 U-0 R/W-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0
PTEN — PTSIDL SESTAT SEIEN EIPU(1) SYNCPOL(1) SYNCOEN(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SYNCEN(1) SYNCSRC<2:0>(1) SEVTPS<3:0>(1)
bit 7 bit 0
Legend: HC = Cleared in Hardware HS = Set in Hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PTEN: PWM Module Enable bit
1 = PWM module is enabled
0 = PWM module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 PTSIDL: PWM Time Base Stop in Idle Mode bit
1 = PWM time base halts in CPU Idle mode
0 = PWM time base runs in CPU Idle mode
bit 12 SESTAT: Special Event Interrupt Status bit
1 = Special Event Interrupt is pending
0 = Special Event Interrupt is not pending
bit 11 SEIEN: Special Event Interrupt Enable bit
1 = Special Event Interrupt is enabled
0 = Special Event Interrupt is disabled
bit 10 EIPU: Enable Immediate Period Updates bit(1)
1 = Active Period register is updated immediately
0 = Active Period register updates occur on PWM cycle boundaries
bit 9 SYNCPOL: Synchronize Input and Output Polarity bit
(1)
1 = SYNCIx/SYNCO polarity is inverted (active-low)
0 = SYNCIx/SYNCO is active-high
bit 8 SYNCOEN: Primary Time Base Sync Enable bit(1)
1 = SYNCO output is enabled
0 = SYNCO output is disabled
bit 7 SYNCEN: External Time Base Synchronization Enable bit(1)
1 = External synchronization of primary time base is enabled
0 = External synchronization of primary time base is disabled
bit 6-4 SYNCSRC<2:0>: Synchronous Source Selection bits(1)
These bits select the SYNCIx or PTGOx input as the synchronous source. Refer to the “High-Speed
PWM” chapter in the specific device data sheet for availability.
bit 3-0 SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits
(1)
1111 = 1:16 postscaler generates Special Event trigger at every 16th compare match event
•
•
•
0001 = 1:2 postscaler generates Special Event trigger at every second compare match event
0000 = 1:1 postscaler generates Special Event trigger at every compare match event
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user
application must program the period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-7
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-4: STCON: PWM Secondary Master Time Base Control Registe (1)
U-0 U-0 U-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — SESTAT SEIEN EIPU(2) SYNCPOL SYNCOEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SYNCEN SYNCSRC<2:0> SEVTPS<3:0>
bit 7 bit 0
Legend: HC = Cleared in Hardware HS = Set in Hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 Unimplemented: Read as ‘0’
bit 12 SESTAT: Special Event Interrupt Status bit
1 = Secondary Special Event Interrupt is pending
0 = Secondary Special Event Interrupt is not pending
bit 11 SEIEN: Special Event Interrupt Enable bit
1 = Secondary Special Event Interrupt is enabled
0 = Secondary Special Event Interrupt is disabled
bit 10 EIPU: Enable Immediate Period Updates bit(2)
1 = Active Secondary Period register is updated immediately
0 = Active Secondary Period register updates occur on PWM cycle boundaries
bit 9 SYNCPOL: Synchronize Input and Output Polarity bit
1 = SYNCO2 output is active-low
0 = SYNCO2 output is active-high
bit 8 SYNCOEN: Secondary Master Time Base Sync Enable bit
1 = SYNCO2 output is enabled
0 = SYNCO2 output is disabled
bit 7 SYNCEN: External Secondary Master Time Base Synchronization Enable bit
1 = External synchronization of secondary time base is enabled
0 = External synchronization of secondary time base is disabled
bit 6-4 SYNCSRC<2:0>: Secondary Time Base Sync Source Selection bits
These bits select the SYNCIx or PTGOx input as the synchronous source. Refer to the “High-Speed
PWM” chapter in the specific device data sheet for availability.
bit 3-0 SEVTPS<3:0>: PWM Secondary Special Event Trigger Output Postscaler Select bits
1111 = 1:16 Postscale
•
•
•
0001 = 1:2 Postscale
0000 = 1:1 Postscale
Note 1: This register is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific
device data sheet for availability.
2: This bit only applies to the secondary master time base period.
dsPIC33E/PIC24E Family Reference Manual
DS70645C-page 14-8 © 2010-2011 Microchip Technology Inc.
Register 14-5: STCON2: PWM Secondary Clock Divider Select Register 2
(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — — — — PCLKDIV<2:0>(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0’
bit 2-0 PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(2)
111 = Reserved
110 = Divide by 64
101 = Divide by 32
100 = Divide by 16
011 = Divide by 8
010 = Divide by 4
001 = Divide by 2
000 = Divide by 1, maximum PWM timing resolution (power-on default)
Note 1: This register is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific
device data sheet for availability.
2: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
© 2010-2011 Microchip Technology Inc. DS70645C-page 14-9
Section 14. High-Speed PWM
High-Speed PWM
14
Register 14-6: STPER: Secondary Master Time Base Period Register
(1)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
STPER<15:8>
bit 15 bit 8
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
STPER<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 STPER<15:0>: Secondary Master Time Base Period Value bits
Note 1: This register is not available on all devices. Refer to the “High-Speed PWM” chapter of the specific
device data sheet for availability.
Register 14-7: MDC: PWM Master Duty Cycle Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MDC<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MDC<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 MDC<15:0>: Master PWM Duty Cycle Value bits
Register 14-8: SEVTCMP: PWM Special Event Compare Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEVTCMP<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEVTCMP<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 SEVTCMP<15:0>: Special Event Compare Count Value bits

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