Microchip MEC1701 Bedienungsanleitung

Microchip Nicht kategorisiert MEC1701

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 2016 Microchip Technology Inc. DS00002295A-page 1
INTRODUCTION
The MEC170x can achieve very low power consumption. The part consumes the lowest power when the part is in heavy
sleep mode, with the 48MHz and EC processor clock turned off, in the S5 system sleep state.
There are several steps that should be taken to ensure that the part consumes the lowest power. These are outlined in
the sections that follow.
This document includes the following topics:
•Pin Considerations on page 2
•Counters/Timers/LEDs on page 2
•Miscellaneous on page 3
•Low Power Guidance on page 3
Audience
This document is written for system engineers who want to achieve a low power design using the MEC170x device.
References
The following document should be referenced when using this application note. See your Microchip representative for
availability.
• MEC170x Data Sheet
AN2295
MEC170x Achieving Low Power Consumption
Author: Tom Rubino

Microchip Technology Inc.
AN2295
DS00002295A-page 2  2016 Microchip Technology Inc.
PIN CONSIDERATIONS
Make sure that no pins are floating. Check all pins in every state (S0, S3, S5).
Inputs:
• Make sure that pins are at a proper voltage.
- Low voltage is below the max Low Input Level.
- High voltage is above the min High Input Level.
- See Section 50.0 “ELECTRICAL SPECIFICATIONS” in the data sheet.
Outputs:
• Use the lowest output current required for the external logic.
• Do not drive outputs high into unpowered chips.
• Remove or reduce any DC Loads.
- Use the weakest pull-up and pull-down resistors required.
- For example, for keyscan pins, using pre-drive mode allows use of weaker pull-up resistors (e.g., 100k
instead of 10k).
To get lowest power, do one of the following for the pins (see Note):
1. Set the pins to output PP and drive high or low.
2. Set the pins to open drain and drive low (a high is the same as a float and causes crowbar current).
3. Set the pins to open drain and drive high – this requires a pull-up resistor to the correct power rail or crowbar
current will result – see the next item.
4. Set the pin to open drain and drive high, but if the pull-up resistor is to an under voltage level – such as a 3.3V
pin to 1.8V pull-up – then the input must be turned off to avoid crowbar current (which is current flowing from the
power rail to ground within the pad).
- This is done by setting bits[3:2], POWER_GATING, in the GPIO pin control register to 11b= VTR Powered
Output Only: Input pad is disabled and output will be tristated when VTR Power Rail is off.
5. Turn off the pin (un-power the pin).
- This is done by setting bits[3:2], POWER_GATING, in the GPIO pin control register to 10b=Unpowered: The
GPIO pad is turned off completely. Both the input buffer and output buffer on the pad are disabled.
COUNTERS/TIMERS/LEDS
Whenever possible, do not enable timers that run off of the 48MHz, since they will prevent the part from going to sleep.
Use 32KHz timers instead.
The following is a list of all 32KHz timer resources:
• WDT
• Hibernation timer
• RTOS timer
• RTC
• Week timer
• Blinking/Breathing LEDs
Note: All functional pins have GPIOs associated with them to allow the configurations described above. The bit
definitions for the GPIO pin control register are shown in Section 18.10.1 “PIN CONTROL REGISTER” in
the data sheet.
- Bit 10, GPIO_OUTPUT_SELECT, determines which register is used to update the data register for GPIO
outputs. GPIO output data for this GPIO comes from bit 16, the ALTERNATE_GPIO_ DATA field of this reg-
ister; or the bit corresponding to this GPIO in the GPIO Output Register.
- Bit 9, GPIO_DIRECTION, controls the buffer direction (input or output) when the pin function is selected as a
GPIO.
- Bit 8, OUTPUT_BUFFER_TYPE, controls the mode of the output buffer (Open Drain or Push-Pull).
 2016 Microchip Technology Inc. DS00002295A-page 3
AN2295
MISCELLANEOUS
Make sure all debug blocks are disabled: JTAG, Trace, ETM, ITM.
Disable unused blocks, e.g., cryptographic hardware blocks.
LOW POWER GUIDANCE
In order to achieve the lowest power cons ntage of the features that allow the EC umption, it is important to take adva
and the chip to go to sleep whenever possible. Some of these features are described below.
Interrupts
In general, use interrupts instead of polling for events. This allows the chip to go to sleep and only wake on an event.
Use Wake-Only Interrupts where possible for the LPC, eSPI and SMBus blocks. These events are listed in GIRQ22.
These are events that are used to wake the sleep interface on traffic, but do not generate an interrupt to the processor.
This allows a block to accept data and only wake the processor if necessary. See Section 4.7.4.1 “Wake-Only Events”
in the data sheet.
Network Layer for SMBus
Use the Network Layer for SMB transactions instead of doing byte-by-byte transactions on SMBus. Doing byte transfers
on SMBus requires the EC to manage the transactions a byte at a time.
Using the network layer utilizes HW that handles the SMBus transactions so that the EC does not have to manage the
transactions. This allows the EC to sleep during the SMBus transactions, and allows for more efficient transactions over
SMBus.
EMI
Use the Embedded Memory Interface (EMI) instead of the ACPI interface or mailbox for passing large blocks or data.
The EMI can be used by the Host to access regions of internal memory directly without requiring any assistance from
the EC.
For example, moving a block of data through the ACPI interface or mailbox requires EC involvement to move the data
to SRAM byte-by-byte and then process the data.
By using EMI, the host can directly access the EC’s SRAM space without assistance from the EC. In this case, the EC
can remain sleeping while the host accesses data and only wakes if the host triggers an interrupt to the EC to process
the data (if required). This allows for more efficient movement of data since the EC is not involved and can be sleeping
while the data is read/written by the host.
Heavy Sleep Mode
Enter Heavy Sleep mode whenever the part is idle.
The 48MHZ_OUT pin can be used to verify the chip’s clock has stopped, which indicates the device is in LIGHT SLEEP
or HEAVY SLEEP, as determined by the System Sleep Control Register.
There are two ways to command the blocks to enter sleep.
1. Assert the SLEEP_ALL bit. See Section 4.9.4 “SYSTEM SLEEP CONTROL REGISTER” in the data sheet.
2. Assert all the individual block sleep enable bits. See Section 4.9.1 “SLEEP ENABLE N REGISTER FORMAT” in
the data sheet.
Note: The SLEEP_ALL bit is automatically cleared when the processor responds to an interrupt. However, the
individual sleep enable bits are not cleared. If the SLEEP_ALL bit is used, set the sleep enable bit for blocks
that are not used – these blocks will not wake after part wakes up.

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Kategorie: Nicht kategorisiert
Modell: MEC1701

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